diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
| commit | c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9 (patch) | |
| tree | 3a6c277e4c65b041de01b7b976a60c245729ec65 /src/arch/mips/locked_mem.hh | |
| parent | c635d04642723f7dea68ee6c6c882c7751d8484b (diff) | |
| download | gem5-c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9.tar.xz | |
MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
Diffstat (limited to 'src/arch/mips/locked_mem.hh')
| -rw-r--r-- | src/arch/mips/locked_mem.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 3c81bc249..2722ce8d2 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -50,8 +50,8 @@ template <class XC> inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); - xc->setMiscRegNoEffect(LLFlag, true); + xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf); + xc->setMiscRegNoEffect(MISCREG_LLADDR, true); DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" " Address set to %x.\n", req->threadId(), req->getPaddr() & ~0xf); @@ -67,14 +67,14 @@ handleLockedWrite(XC *xc, Request *req) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscRegNoEffect(LLFlag); - Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); + bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG); + Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscRegNoEffect(LLFlag, false); + xc->setMiscRegNoEffect(MISCREG_LLFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect |