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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/mips/mt.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/mips/mt.hh')
| -rwxr-xr-x | src/arch/mips/mt.hh | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index cc72d7a5d..7b28b0493 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -113,24 +113,25 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) int success = 0; for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) { TCBindReg tidTCBind = - tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid); + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), tid); TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); if (tidTCBind.curVPE == tcBind.curVPE) { TCStatusReg tidTCStatus = - tc->readRegOtherThread(MISCREG_TC_STATUS + - Misc_Reg_Base,tid); + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), + tid); TCHaltReg tidTCHalt = - tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid); + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT), + tid); if (tidTCStatus.da == 1 && tidTCHalt.h == 0 && tidTCStatus.a == 0 && success == 0) { - tc->setRegOtherThread(MISCREG_TC_RESTART + - Misc_Reg_Base, Rs, tid); - tc->setRegOtherThread(Rd_bits, Rt, tid); + tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_RESTART), + Rs, tid); + tc->setRegOtherThread(RegId(IntRegClass, Rd_bits), Rt, tid); StatusReg status = tc->readMiscReg(MISCREG_STATUS); TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS); @@ -149,7 +150,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) tidTCStatus.asid = tcStatus.asid; // Write Status Register - tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base, + tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), tidTCStatus, tid); // Mark As Successful Fork @@ -185,13 +186,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) for (ThreadID tid = 0; tid < num_threads; tid++) { TCStatusReg tidTCStatus = - tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base, + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS), tid); TCHaltReg tidTCHalt = - tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base, + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT), tid); TCBindReg tidTCBind = - tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, + tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), tid); if (tidTCBind.curVPE == tcBind.curVPE && |