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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/arch/mips/regfile.cc | |
parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/arch/mips/regfile.cc')
-rw-r--r-- | src/arch/mips/regfile.cc | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc index 0c670af6d..663115bb6 100644 --- a/src/arch/mips/regfile.cc +++ b/src/arch/mips/regfile.cc @@ -188,12 +188,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string §ion) } - -void RegFile::changeContext(RegContextParam param, RegContextVal val) -{ - panic("Change Context Not Implemented for MipsISA"); -} - static inline int flattenIntIndex(ThreadContext * tc, int reg) { return reg; @@ -206,12 +200,6 @@ MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) } void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest); -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) { panic("Copy Misc. Regs Not Implemented Yet\n"); |