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author | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:07:15 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:07:15 -0400 |
commit | 74546aac0124a5ba09a0e6bfef18dc3e0b7509b8 (patch) | |
tree | 367e2fbfa58d670c2a91076f080c998e69f4eeb6 /src/arch/mips/regfile/float_regfile.hh | |
parent | 741bc40cc336be6afdff73a230eaec980812b7d5 (diff) | |
download | gem5-74546aac0124a5ba09a0e6bfef18dc3e0b7509b8.tar.xz |
Cleaned up include files and got rid of many using directives in header files.
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
Diffstat (limited to 'src/arch/mips/regfile/float_regfile.hh')
-rw-r--r-- | src/arch/mips/regfile/float_regfile.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index e9447d39e..ce5f1fdde 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -139,7 +139,6 @@ namespace MipsISA Fault setReg(int floatReg, const FloatRegVal &val, int width) { - using namespace std; switch(width) { case SingleWidth: @@ -168,7 +167,6 @@ namespace MipsISA Fault setRegBits(int floatReg, const FloatRegBits &val, int width) { - using namespace std; switch(width) { |