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author | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
commit | 753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch) | |
tree | 9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/arch/mips/regfile/float_regfile.hh | |
parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
download | gem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz |
mips import pt. 1
src/arch/mips/SConscript:
"mips import pt.1".
--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/arch/mips/regfile/float_regfile.hh')
-rw-r--r-- | src/arch/mips/regfile/float_regfile.hh | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index ce5f1fdde..21c16c238 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -88,12 +88,9 @@ namespace MipsISA public: - void clear() - { - bzero(regs, sizeof(regs)); - } + void clear() { bzero(®s, sizeof(regs)); } - double readReg(int floatReg, int width) + double readReg(int floatReg, int width, unsigned tid = 0) { switch(width) { @@ -115,7 +112,7 @@ namespace MipsISA } } - FloatRegBits readRegBits(int floatReg, int width) + FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0) { if (floatReg < NumFloatArchRegs - 1) { switch(width) @@ -137,8 +134,9 @@ namespace MipsISA } } - Fault setReg(int floatReg, const FloatRegVal &val, int width) + Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0) { + using namespace std; switch(width) { case SingleWidth: @@ -165,8 +163,9 @@ namespace MipsISA return NoFault; } - Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0) { + using namespace std; switch(width) { |