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author | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
commit | 753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch) | |
tree | 9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/arch/mips/regfile/int_regfile.hh | |
parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
download | gem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz |
mips import pt. 1
src/arch/mips/SConscript:
"mips import pt.1".
--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/arch/mips/regfile/int_regfile.hh')
-rw-r--r-- | src/arch/mips/regfile/int_regfile.hh | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index a45a17a85..2a034ad8d 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -47,8 +47,21 @@ namespace MipsISA } enum MiscIntRegNums { - HI = NumIntArchRegs, - LO + LO = NumIntArchRegs, + HI, + DSPACX0, + DSPLo1, + DSPHi1, + DSPACX1, + DSPLo2, + DSPHi2, + DSPACX2, + DSPLo3, + DSPHi3, + DSPACX3, + DSPControl, + DSPLo0 = LO, + DSPHi0 = HI }; class IntRegFile @@ -57,6 +70,8 @@ namespace MipsISA IntReg regs[NumIntRegs]; public: + void clear() { bzero(®s, sizeof(regs)); } + IntReg readReg(int intReg) { return regs[intReg]; @@ -64,7 +79,10 @@ namespace MipsISA Fault setReg(int intReg, const IntReg &val) { - regs[intReg] = val; + if (intReg != ZeroReg) { + regs[intReg] = val; + } + return NoFault; } |