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authorGabe Black <gblack@eecs.umich.edu>2007-08-01 15:12:07 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-01 15:12:07 -0700
commit8da3e0548e76795f74af5ff8f4ffadf3d0b5191b (patch)
treefb80d3ba61318edbc1484c70f524133a64981618 /src/arch/mips/regfile/misc_regfile.hh
parentc4c8a121863fcbde7ba67823f06a3f7564c27cba (diff)
parent84cd78e96f892f52a715cfe10d9405987f5e9ba1 (diff)
downloadgem5-8da3e0548e76795f74af5ff8f4ffadf3d0b5191b.tar.xz
Merge with head.
--HG-- extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
Diffstat (limited to 'src/arch/mips/regfile/misc_regfile.hh')
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 54b086a8b..0846378bb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -33,14 +33,12 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
-#include "base/bitfield.hh"
-#include "cpu/base.hh"
+#include "sim/eventq.hh"
#include "sim/faults.hh"
#include <queue>
class ThreadContext;
+class BaseCPU;
namespace MipsISA
{
@@ -76,7 +74,10 @@ namespace MipsISA
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc);
+ void copyMiscRegs(ThreadContext *tc)
+ {
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+ }
inline unsigned getVPENum(unsigned tid);