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authorKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
commit269259004943b80916ec9b6354f2fc00c811c88b (patch)
tree4a01b0300aef6692a787f85d42280a1dbdb086e6 /src/arch/mips/regfile/misc_regfile.hh
parent422ab8bec0034a6b703578ec2c92350c6382875a (diff)
downloadgem5-269259004943b80916ec9b6354f2fc00c811c88b.tar.xz
Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
Diffstat (limited to 'src/arch/mips/regfile/misc_regfile.hh')
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh25
1 files changed, 16 insertions, 9 deletions
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 0846378bb..a92215076 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
+ * Jaidev Patwardhan
*/
#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
@@ -33,11 +34,13 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "base/bitfield.hh"
#include "sim/eventq.hh"
-#include "sim/faults.hh"
#include <queue>
-class ThreadContext;
+class Params;
class BaseCPU;
namespace MipsISA
@@ -58,6 +61,7 @@ namespace MipsISA
};
std::vector<std::vector<MiscReg> > miscRegFile;
+ std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
std::vector<BankType> bankType;
BaseCPU *cpu;
@@ -70,15 +74,10 @@ namespace MipsISA
void clear(unsigned tid_or_vpn = 0);
- void reset(std::string core_name, unsigned num_threads, unsigned num_vpes);
+ void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc)
- {
- panic("Copy Misc. Regs Not Implemented Yet\n");
- }
-
inline unsigned getVPENum(unsigned tid);
//////////////////////////////////////////////////////////
@@ -91,14 +90,22 @@ namespace MipsISA
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, unsigned tid) { }
MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+
+ //template <class TC>
MiscReg readReg(int misc_reg,
ThreadContext *tc, unsigned tid = 0);
- MiscReg filterCP0Write(int misc_reg, MiscReg val) { return val; }
+ MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
+ void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+
+ //template <class TC>
void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, unsigned tid = 0);
+ int getInstAsid();
+ int getDataAsid();
+
//////////////////////////////////////////////////////////
//
// DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)