summaryrefslogtreecommitdiff
path: root/src/arch/mips/regfile/misc_regfile.hh
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-06-12 00:49:24 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-06-12 00:49:24 -0400
commit15a8f050605919579e81b6abb98a0b596334216d (patch)
tree583b0b30f13d9874a69015d58d041ce2d7352960 /src/arch/mips/regfile/misc_regfile.hh
parent60a734e1750f3c051fe92fea6f12158db6e2dcb9 (diff)
parentdf4b4f001e4db902297acf3b75480e4886e4e882 (diff)
downloadgem5-15a8f050605919579e81b6abb98a0b596334216d.tar.xz
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem src/arch/sparc/regfile.hh: Hand Merge --HG-- extra : convert_revision : c47202689202069892524a7d71962082469996ee
Diffstat (limited to 'src/arch/mips/regfile/misc_regfile.hh')
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 9f054e5f7..f8aeab8cb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -24,6 +24,8 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
*/
#ifndef __ARCH_MIPS_MISC_REGFILE_HH__
@@ -34,7 +36,7 @@
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
@@ -55,14 +57,14 @@ namespace MipsISA
int getInstAsid();
int getDataAsid();
- void copyMiscRegs(ExecContext *xc);
+ void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)
{
return miscRegFile[misc_reg];
}
- MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
{
return miscRegFile[misc_reg];
}
@@ -73,7 +75,7 @@ namespace MipsISA
}
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
- ExecContext *xc)
+ ThreadContext *tc)
{
miscRegFile[misc_reg] = val; return NoFault;
}
@@ -85,9 +87,9 @@ namespace MipsISA
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
- MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
+ MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
- Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
+ Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
#endif
friend class RegFile;
};