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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit301df68c73b5903abc3d7d486a76ac63235bb7a2 (patch)
treecceb984b30043202836bb9563632731a73e77410 /src/arch/mips/regfile/regfile.hh
parent27b6148f47676c5c95022b3dcd606ceea4611818 (diff)
downloadgem5-301df68c73b5903abc3d7d486a76ac63235bb7a2.tar.xz
MIPS: Phase out MIPS's int_regfile.hh.
Diffstat (limited to 'src/arch/mips/regfile/regfile.hh')
-rw-r--r--src/arch/mips/regfile/regfile.hh25
1 files changed, 24 insertions, 1 deletions
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 061b4a07d..28d295022 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -35,7 +35,6 @@
#include "arch/mips/types.hh"
#include "arch/mips/isa_traits.hh"
//#include "arch/mips/mt.hh"
-#include "arch/mips/regfile/int_regfile.hh"
//#include "cpu/base.hh"
#include "sim/faults.hh"
@@ -71,6 +70,30 @@ namespace MipsISA
Cause_Field = 11
};
+ enum MiscIntRegNums {
+ LO = NumIntArchRegs,
+ HI,
+ DSPACX0,
+ DSPLo1,
+ DSPHi1,
+ DSPACX1,
+ DSPLo2,
+ DSPHi2,
+ DSPACX2,
+ DSPLo3,
+ DSPHi3,
+ DSPACX3,
+ DSPControl,
+ DSPLo0 = LO,
+ DSPHi0 = HI
+ };
+
+ //@TODO: Implementing ShadowSets needs to
+ //edit this value such that:
+ //TotalArchRegs = NumIntArchRegs * ShadowSets
+ const int TotalArchRegs = NumIntArchRegs;
+
+
class RegFile {
protected:
Addr pc; // program counter