Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

1 files changed, 37 insertions, 128 deletions

diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 4be8d399c..7d100a905 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,147 +32,71 @@
 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
 
 #include "arch/mips/types.hh"
+#include "arch/mips/isa_traits.hh"
+//#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
 #include "arch/mips/regfile/float_regfile.hh"
 #include "arch/mips/regfile/misc_regfile.hh"
+//#include "cpu/base.hh"
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ThreadContext;
+class BaseCPU;
 
 namespace MipsISA
 {
     class RegFile {
       protected:
+        Addr pc;			// program counter
+        Addr npc;			// next-cycle program counter
+        Addr nnpc;			// next-next-cycle program counter
+                                        // used to implement branch delay slot
+                                        // not real register
+
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
         MiscRegFile miscRegFile;	// control register file
 
       public:
-        void clear()
-        {
-            intRegFile.clear();
-            floatRegFile.clear();
-            miscRegFile.clear();
-        }
+        void clear();
+        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
+        MiscRegFile *getMiscRegFilePtr();
 
-        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
-        {
-            bzero(&intRegFile, sizeof(intRegFile));
-            bzero(&floatRegFile, sizeof(floatRegFile));
-            miscRegFile.reset(core_name, num_threads, num_vpes);
-        }
+        IntReg readIntReg(int intReg);
+        Fault setIntReg(int intReg, const IntReg &val);
 
-        IntReg readIntReg(int intReg)
-        {
-            return intRegFile.readReg(intReg);
-        }
-
-        Fault setIntReg(int intReg, const IntReg &val)
-        {
-            return intRegFile.setReg(intReg, val);
-        }
-
-        MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0)
-        {
-            return miscRegFile.readRegNoEffect(miscReg, tid);
-        }
 
+        MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
         MiscReg readMiscReg(int miscReg, ThreadContext *tc,
-                                      unsigned tid = 0)
-        {
-            return miscRegFile.readReg(miscReg, tc, tid);
-        }
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
-        {
-            miscRegFile.setRegNoEffect(miscReg, val, tid);
-        }
-
+                            unsigned tid = 0);
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
         void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc, unsigned tid = 0)
-        {
-            miscRegFile.setReg(miscReg, val, tc, tid);
-        }
-
-        FloatRegVal readFloatReg(int floatReg)
-        {
-            return floatRegFile.readReg(floatReg,SingleWidth);
-        }
-
-        FloatRegVal readFloatReg(int floatReg, int width)
-        {
-            return floatRegFile.readReg(floatReg,width);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg)
-        {
-            return floatRegFile.readRegBits(floatReg,SingleWidth);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg, int width)
-        {
-            return floatRegFile.readRegBits(floatReg,width);
-        }
+                        ThreadContext * tc, unsigned tid = 0);
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val)
-        {
-            return floatRegFile.setReg(floatReg, val, SingleWidth);
-        }
+        FloatRegVal readFloatReg(int floatReg);
+        FloatRegVal readFloatReg(int floatReg, int width);
+        FloatRegBits readFloatRegBits(int floatReg);
+        FloatRegBits readFloatRegBits(int floatReg, int width);
+        Fault setFloatReg(int floatReg, const FloatRegVal &val);
+        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width);
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
-        {
-            return floatRegFile.setReg(floatReg, val, width);
-        }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
-        {
-            return floatRegFile.setRegBits(floatReg, val, SingleWidth);
-        }
+        void setShadowSet(int css);
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-        {
-            return floatRegFile.setRegBits(floatReg, val, width);
-        }
-
-      protected:
-
-        Addr pc;			// program counter
-        Addr npc;			// next-cycle program counter
-        Addr nnpc;			// next-next-cycle program counter
-                                        // used to implement branch delay slot
-                                        // not real register
+        int instAsid();
+        int dataAsid();
 
       public:
-        Addr readPC()
-        {
-            return pc;
-        }
+        Addr readPC();
+        void setPC(Addr val);
 
-        void setPC(Addr val)
-        {
-            pc = val;
-        }
-
-        Addr readNextPC()
-        {
-            return npc;
-        }
-
-        void setNextPC(Addr val)
-        {
-            npc = val;
-        }
-
-        Addr readNextNPC()
-        {
-            return nnpc;
-        }
+        Addr readNextPC();
+        void setNextPC(Addr val);
 
-        void setNextNPC(Addr val)
-        {
-            nnpc = val;
-        }
+        Addr readNextNPC();
+        void setNextNPC(Addr val);
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
@@ -180,23 +104,8 @@ namespace MipsISA
         void changeContext(RegContextParam param, RegContextVal val)
         {
         }
-    };
 
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    void
-    copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    void
-    copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+    };
 
 } // namespace MipsISA