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authorGabe Black <gblack@eecs.umich.edu>2007-08-01 13:55:47 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-01 13:55:47 -0700
commit239d124e8339b254495df45df89fc249ae217d73 (patch)
treef05e14dc2b315892c7bc067691ad4325b9b499d5 /src/arch/mips/regfile
parente5e5b0119d6219782c834d29a63a7bb152a68dc5 (diff)
downloadgem5-239d124e8339b254495df45df89fc249ae217d73.tar.xz
MIPS: Cleaned up includes to break loops, and got rid of isa_traits.cc
Loops of header files including each other was causing compilation to fail. To fix it, a bunch of unnecessary includes were removed, and the code in isa_traits.cc which brought a bunch of include chains together was broken up and put in proximity to the header files that delcared it. --HG-- extra : convert_revision : 66ef7762024b72bb91147a5589a0779e279521e0
Diffstat (limited to 'src/arch/mips/regfile')
-rwxr-xr-xsrc/arch/mips/regfile/misc_regfile.cc8
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh11
-rw-r--r--src/arch/mips/regfile/regfile.hh8
3 files changed, 14 insertions, 13 deletions
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index c97d93cf9..8f8899e92 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -30,13 +30,13 @@
#include "base/bitfield.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
-#include "arch/mips/mt_constants.hh"
#include "arch/mips/faults.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
-#include "cpu/thread_context.hh"
#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
+#include "cpu/thread_context.hh"
//#include "cpu/mixie/cpu.hh"
using namespace std;
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 54b086a8b..0846378bb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -33,14 +33,12 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
-#include "base/bitfield.hh"
-#include "cpu/base.hh"
+#include "sim/eventq.hh"
#include "sim/faults.hh"
#include <queue>
class ThreadContext;
+class BaseCPU;
namespace MipsISA
{
@@ -76,7 +74,10 @@ namespace MipsISA
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc);
+ void copyMiscRegs(ThreadContext *tc)
+ {
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+ }
inline unsigned getVPENum(unsigned tid);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index f13653132..b83bb576b 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,8 +32,6 @@
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
@@ -189,9 +187,11 @@ namespace MipsISA
return reg;
}
- void copyRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyMiscRegs(ThreadContext *src, ThreadContext *dest);
} // namespace MipsISA