Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults

--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675

2 files changed, 21 insertions, 23 deletions

diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index a4527a203..368925e00 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -220,20 +220,20 @@ namespace MipsISA
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
+        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
 
-        Fault setReg(int misc_reg, const MiscReg &val)
+        void setReg(int misc_reg, const MiscReg &val)
         {
-            miscRegFile[misc_reg] = val; return NoFault;
+            miscRegFile[misc_reg] = val;
         }
 
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setRegWithEffect(int misc_reg, const MiscReg &val,
                                ThreadContext *tc)
         {
-            miscRegFile[misc_reg] = val; return NoFault;
+            miscRegFile[misc_reg] = val;
         }
 
         friend class RegFile;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 3a18c681b..dee883c4a 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -62,22 +62,20 @@ namespace MipsISA
             return miscRegFile.readReg(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ThreadContext *tc)
+        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
         {
-            fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+            return miscRegFile.readRegWithEffect(miscReg, tc);
         }
 
-        Fault setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscReg(int miscReg, const MiscReg &val)
         {
-            return miscRegFile.setReg(miscReg, val);
+            miscRegFile.setReg(miscReg, val);
         }
 
-        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)
@@ -100,24 +98,24 @@ namespace MipsISA
             return floatRegFile.readRegBits(floatReg,width);
         }
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val)
+        void setFloatReg(int floatReg, const FloatRegVal &val)
         {
-            return floatRegFile.setReg(floatReg, val, SingleWidth);
+            floatRegFile.setReg(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
+        void setFloatReg(int floatReg, const FloatRegVal &val, int width)
         {
-            return floatRegFile.setReg(floatReg, val, width);
+            floatRegFile.setReg(floatReg, val, width);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
-            return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+            floatRegFile.setRegBits(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
         {
-            return floatRegFile.setRegBits(floatReg, val, width);
+            floatRegFile.setRegBits(floatReg, val, width);
         }
 
         IntReg readIntReg(int intReg)
@@ -125,9 +123,9 @@ namespace MipsISA
             return intRegFile.readReg(intReg);
         }
 
-        Fault setIntReg(int intReg, const IntReg &val)
+        void setIntReg(int intReg, const IntReg &val)
         {
-            return intRegFile.setReg(intReg, val);
+            intRegFile.setReg(intReg, val);
         }
       protected: