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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch)
tree0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/arch/mips/regfile
parent3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff)
downloadgem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
Diffstat (limited to 'src/arch/mips/regfile')
-rw-r--r--src/arch/mips/regfile/regfile.cc47
-rw-r--r--src/arch/mips/regfile/regfile.hh14
2 files changed, 0 insertions, 61 deletions
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index 975fad963..2b70ea9bd 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -42,7 +42,6 @@ RegFile::clear()
{
intRegFile.clear();
floatRegFile.clear();
- miscRegFile.clear();
}
void
@@ -51,7 +50,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
- miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
}
IntReg
@@ -66,31 +64,6 @@ RegFile::setIntReg(int intReg, const IntReg &val)
return intRegFile.setReg(intReg, val);
}
-MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
-{
- return miscRegFile.readRegNoEffect(miscReg, tid);
-}
-
-MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
-{
- return miscRegFile.readReg(miscReg, tc, tid);
-}
-
-void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
-{
- miscRegFile.setRegNoEffect(miscReg, val, tid);
-}
-
-void
-RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid)
-{
- miscRegFile.setReg(miscReg, val, tc, tid);
-}
-
FloatRegVal
RegFile::readFloatReg(int floatReg)
{
@@ -144,17 +117,6 @@ RegFile::setShadowSet(int css){
intRegFile.setShadowSet(css);
}
-int
-RegFile::instAsid()
-{
- return miscRegFile.getInstAsid();
-}
-
-int
-RegFile::dataAsid()
-{
- return miscRegFile.getDataAsid();
-}
Addr
RegFile::readPC()
@@ -197,10 +159,6 @@ RegFile::serialize(EventManager *em, std::ostream &os)
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
- //SERIALZE_ARRAY(miscRegFile);
- //SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.lock_flag);
- //SERIALIZE_SCALAR(miscRegs.lock_addr);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
@@ -212,14 +170,9 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp,
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile);
- //UNSERIALZE_ARRAY(miscRegFile);
- //UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
- //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
-
}
} // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 91951b078..b05f513b4 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -37,7 +37,6 @@
//#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
//#include "cpu/base.hh"
#include "sim/faults.hh"
@@ -57,26 +56,16 @@ namespace MipsISA
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
void clear();
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu);
- MiscRegFile *getMiscRegFilePtr();
IntReg readIntReg(int intReg);
Fault setIntReg(int intReg, const IntReg &val);
- MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
- MiscReg readMiscReg(int miscReg, ThreadContext *tc,
- ThreadID tid = 0);
- void setMiscRegNoEffect(int miscReg, const MiscReg &val,
- ThreadID tid = 0);
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid = 0);
-
FloatRegVal readFloatReg(int floatReg);
FloatRegVal readFloatReg(int floatReg, int width);
FloatRegBits readFloatRegBits(int floatReg);
@@ -89,9 +78,6 @@ namespace MipsISA
void setShadowSet(int css);
- int instAsid();
- int dataAsid();
-
public:
Addr readPC();
void setPC(Addr val);