next round of MIPS ISA changes

src/arch/mips/isa/decoder.isa:
    div,divu,ext,seb,seh, fp conditonal moves, fp indexed memory...
src/arch/mips/isa/formats/mem.isa:
    MemoryNoDisp class .. use sext<> function instead of doing it manually
src/arch/mips/regfile/float_regfile.hh:
    use bits function

--HG--
extra : convert_revision : cbbda9499185b91bdb2a6198fe1b961be04f9265

1 files changed, 7 insertions, 7 deletions

diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index d1a60298a..e260f681c 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_FLOAT_REGFILE_HH__
@@ -34,13 +32,14 @@
 #include "arch/mips/types.hh"
 #include "arch/mips/constants.hh"
 #include "base/misc.hh"
+#include "base/bitfield.hh"
 #include "config/full_system.hh"
 #include "sim/byteswap.hh"
 #include "sim/faults.hh"
 #include "sim/host.hh"
 
 class Checkpoint;
-class ThreadContext;
+class ExecContext;
 class Regfile;
 
 namespace MipsISA
@@ -103,6 +102,7 @@ namespace MipsISA
 
         Fault setReg(int floatReg, const FloatReg &val, int width)
         {
+            using namespace std;
             switch(width)
             {
               case SingleWidth:
@@ -117,8 +117,8 @@ namespace MipsISA
                 {
                     const void *double_ptr = &val;
                     FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-                    regs[floatReg + 1] = temp_double >> 32;
-                    regs[floatReg] = 0x0000FFFF & temp_double;
+                    regs[floatReg + 1] = bits(temp_double, 63, 32);
+                    regs[floatReg] = bits(temp_double, 31, 0);
                     break;
                 }
 
@@ -140,8 +140,8 @@ namespace MipsISA
                 break;
 
               case DoubleWidth:
-                regs[floatReg + 1] = val >> 32;
-                regs[floatReg] = val;
+                regs[floatReg + 1] = bits(val, 63, 32);
+                regs[floatReg] = bits(val, 31, 0);
                 break;
 
               default: