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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/arch/mips/registers.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/arch/mips/registers.hh')
-rw-r--r-- | src/arch/mips/registers.hh | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index e7d5e346c..0ac84cc7f 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -55,7 +55,6 @@ const int MaxShadowRegSets = 16; // Maximum number of shadow register sets const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// const int NumCCRegs = 0; -const int NumVectorRegs = 0; const uint32_t MIPS32_QNAN = 0x7fbfffff; const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); @@ -279,8 +278,7 @@ const int NumMiscRegs = MISCREG_NUMREGS; // These help enumerate all the registers for dependence tracking. const int FP_Reg_Base = NumIntRegs; const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; -const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 -const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; +const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; @@ -299,12 +297,6 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; -// vector register file entry type -typedef uint64_t VectorRegElement; -const int NumVectorRegElements = 0; -const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); -typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; - typedef union { IntReg intreg; FloatReg fpreg; |