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authorGabe Black <gblack@eecs.umich.edu>2009-07-21 23:38:26 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-21 23:38:26 -0700
commitc874bfae3fd8dfeb05f4b35eba614ffe0145dfa9 (patch)
tree3a6c277e4c65b041de01b7b976a60c245729ec65 /src/arch/mips/tlb.cc
parentc635d04642723f7dea68ee6c6c882c7751d8484b (diff)
downloadgem5-c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9.tar.xz
MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
Diffstat (limited to 'src/arch/mips/tlb.cc')
-rw-r--r--src/arch/mips/tlb.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 37c1ecee3..e01c06ae5 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -311,7 +311,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
if (IsKSeg0(req->getVaddr())) {
// Address will not be translated through TLB, set response, and go!
req->setPaddr(KSeg02Phys(req->getVaddr()));
- if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel ||
+ if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
req->isMisaligned()) {
AddressErrorFault *Flt = new AddressErrorFault();
/* BadVAddr must be set */
@@ -386,7 +386,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
}
} else {
// Didn't find any match, return a TLB Refill Exception
- ItbRefillFault *Flt=new ItbRefillFault();
+ ItbRefillFault *Flt = new ItbRefillFault();
/* EntryHi VPN, ASID fields must be set */
Flt->entryHiAsid = Asid;
Flt->entryHiVPN2 = (VPN >> 2);
@@ -431,7 +431,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
if (IsKSeg0(req->getVaddr())) {
// Address will not be translated through TLB, set response, and go!
req->setPaddr(KSeg02Phys(req->getVaddr()));
- if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel ||
+ if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
req->isMisaligned()) {
StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
/* BadVAddr must be set */