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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
| tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/arch/mips/tlb.cc | |
| parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
| download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz | |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/mips/tlb.cc')
| -rw-r--r-- | src/arch/mips/tlb.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index a18149dfa..46e250b2b 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -142,7 +142,7 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const } inline Fault -TLB::checkCacheability(RequestPtr &req) +TLB::checkCacheability(const RequestPtr &req) { Addr VAddrUncacheable = 0xA0000000; // In MIPS, cacheability is controlled by certain bits of the virtual @@ -282,7 +282,7 @@ TLB::regStats() } Fault -TLB::translateInst(RequestPtr req, ThreadContext *tc) +TLB::translateInst(const RequestPtr &req, ThreadContext *tc) { if (FullSystem) panic("translateInst not implemented in MIPS.\n"); @@ -297,7 +297,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } Fault -TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) +TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) { if (FullSystem) panic("translateData not implemented in MIPS.\n"); @@ -312,7 +312,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) { if (mode == Execute) return translateInst(req, tc); @@ -321,7 +321,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) } void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, +TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) { assert(translation); @@ -329,7 +329,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, } Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +TLB::finalizePhysical(const RequestPtr &req, + ThreadContext *tc, Mode mode) const { return NoFault; } |