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authorGabe Black <gblack@eecs.umich.edu>2011-10-16 05:06:40 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-10-16 05:06:40 -0700
commitbcf664e5f922bf1f1cbdb4bed493a441f82df7f7 (patch)
tree601d76ca3dec31adf8aca23a5bf7e8bb25c0c6ab /src/arch/mips/tlb.hh
parent6ba3ebae43bbc7267e7f013bed949cc3339f0308 (diff)
downloadgem5-bcf664e5f922bf1f1cbdb4bed493a441f82df7f7.tar.xz
SE/FS: Turn on the page table class in FS.
Diffstat (limited to 'src/arch/mips/tlb.hh')
-rw-r--r--src/arch/mips/tlb.hh27
1 files changed, 0 insertions, 27 deletions
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4b1456862..834431536 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -55,33 +55,6 @@ class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string &section)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected: