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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/arch/mips/utility.cc | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/arch/mips/utility.cc')
| -rw-r--r-- | src/arch/mips/utility.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 92ca8c6f0..80047fbfd 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -252,9 +252,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); - // Copy vector registers when vector registers put to use. - assert(NumVectorRegs == 0); - // Copy misc. registers for (int i = 0; i < NumMiscRegs; i++) dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); |