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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
| commit | c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9 (patch) | |
| tree | 3a6c277e4c65b041de01b7b976a60c245729ec65 /src/arch/mips/utility.hh | |
| parent | c635d04642723f7dea68ee6c6c882c7751d8484b (diff) | |
| download | gem5-c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9.tar.xz | |
MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
Diffstat (limited to 'src/arch/mips/utility.hh')
| -rw-r--r-- | src/arch/mips/utility.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 37cd838e5..1e58238e9 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -66,8 +66,8 @@ bool isSnan(void *val_ptr, int size); static inline bool inUserMode(ThreadContext *tc) { - MiscReg Stat = tc->readMiscReg(MipsISA::Status); - MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); + MiscReg Stat = tc->readMiscReg(MISCREG_STATUS); + MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG); if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible |