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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-22 11:16:40 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-22 11:16:40 -0800
commit63a25a56ccc93c24703fec87f830c833974e7060 (patch)
treea0f12244a32eb7da2963ca974ab49a993aee2cfc /src/arch/mips
parent8ea71c3907a411de9c203b45bfd6eab24e3ad849 (diff)
parent77eed184f529c4ccbef59ad2018d18ff3fbb54af (diff)
downloadgem5-63a25a56ccc93c24703fec87f830c833974e7060.tar.xz
m5: merged in hammer fix
Diffstat (limited to 'src/arch/mips')
-rw-r--r--src/arch/mips/isa/decoder.isa16
1 files changed, 1 insertions, 15 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 173fa89df..d97a141de 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -367,21 +367,7 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x1: addiu({{ Rt.sw = Rs.sw + imm; }});
0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }});
-
- //Edited to include MIPS AVP Pass/Fail instructions and
- //default to the sltiu instruction
- 0x3: decode RS_RT_INTIMM {
- 0xabc1: BasicOp::fail({{
- exitSimLoop("AVP/SRVP Test Failed");
- }});
- 0xabc2: BasicOp::pass({{
- exitSimLoop("AVP/SRVP Test Passed");
- }});
- default: sltiu({{
- Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;
- }});
- }
-
+ 0x3: sltiu({{ Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;}});
0x4: andi({{ Rt.sw = Rs.sw & zextImm; }});
0x5: ori({{ Rt.sw = Rs.sw | zextImm; }});
0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }});