diff options
| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
| commit | c75ff71139d6358678835cca63e35d1135eaf466 (patch) | |
| tree | 0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/arch/mips | |
| parent | d99deff8ea296fd28b48da08aba577a1e7dfc01b (diff) | |
| download | gem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz | |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/locked_mem.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index a5ff467b3..a1d89de99 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -79,9 +79,9 @@ handleLockedRead(XC *xc, Request *req) { xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf); xc->setMiscReg(MISCREG_LLFLAG, true); - DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" + DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link" " Address set to %x.\n", - req->threadId(), req->getPaddr() & ~0xf); + req->contextId(), req->getPaddr() & ~0xf); } template <class XC> @@ -123,13 +123,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) } if (!lock_flag){ - DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " + DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, " "Store Conditional Failed.\n", - req->threadId()); + req->contextId()); } else if ((req->getPaddr() & ~0xf) != lock_addr) { - DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, " + DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, " "Store Conditional Failed.\n", - req->threadId()); + req->contextId()); } // store conditional failed already, so don't issue it to mem return false; |