gcc: Add extra parens to quell warnings.

Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.

4 files changed, 18 insertions, 18 deletions

diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index fc3ae65d6..6e4f7afea 100755
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -923,10 +923,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
 
     for (int i = 0; i<2; i++) {
         r_values[i] =
-            dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
         r_values[i + 2] =
-            dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
     }
 
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index b1cd03ca1..0a12c4f6e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -416,16 +416,16 @@ decode OPCODE_HI default Unknown::unknown() {
                                                                                Ctrl_Base_DepTag);
                                                  break;
                                                case 25:
-                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
-                                                          | fcsr_val & 0x00800000 >> 23;
+                                                 data = (fcsr_val & 0xFE000000 >> 24)
+                                                     | (fcsr_val & 0x00800000 >> 23);
                                                  break;
                                                case 26:
-                                                 data = 0 | fcsr_val & 0x0003F07C;
+                                                 data = fcsr_val & 0x0003F07C;
                                                  break;
                                                case 28:
-                                                 data = 0 | fcsr_val & 0x00000F80
-                                                          | fcsr_val & 0x01000000 >> 21
-                                                          | fcsr_val & 0x00000003;
+                                                 data = (fcsr_val & 0x00000F80)
+                                                     | (fcsr_val & 0x01000000 >> 21)
+                                                     | (fcsr_val & 0x00000003);
                                                  break;
                                                case 31:
                                                  data = fcsr_val;
@@ -1963,7 +1963,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: decode OP_LO {
                         format IntOp {
                             0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
-                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
+                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }});
                         }
                     }
                     0x2: decode OP_LO {
@@ -2050,11 +2050,11 @@ decode OPCODE_HI default Unknown::unknown() {
         format LoadUnalignedMemory {
             0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
                         Rt.uw = mem_word << mem_shift |
-                        Rt.uw & mask(mem_shift);
+                            (Rt.uw & mask(mem_shift));
                      }});
             0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
-                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
-                        mem_word >> mem_shift;
+                        Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
+                            (mem_word >> mem_shift);
                      }});
       }
     }
@@ -2069,12 +2069,12 @@ decode OPCODE_HI default Unknown::unknown() {
         format StoreUnalignedMemory {
             0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
                         uint32_t mem_shift = 32 - reg_shift;
-                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
-                                   Rt.uw >> reg_shift;
+                        mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
+                            (Rt.uw >> reg_shift);
                      }});
             0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
                         mem_word = Rt.uw << reg_shift |
-                                   mem_word & (mask(reg_shift));
+                            (mem_word & (mask(reg_shift)));
                      }});
         }
         format CP0Control {
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 8c43a7b0c..bbed94194 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -59,9 +59,9 @@ namespace MipsISA {
         Addr level3() const
         { return MipsISA::PteAddr(addr >> PageShift); }
         Addr level2() const
-        { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
+        { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
         Addr level1() const
-        { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+        { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
     };
 
     // ITB/DTB page table entry
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 36cf76c67..1985c0f43 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -145,7 +145,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
-    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
            cc_val << cc_idx |
            bits(fcsr, cc_idx - 1, 0);