Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

11 files changed, 62 insertions, 62 deletions

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index fa7275908..810c3fed4 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -29,7 +29,7 @@
  */
 
 #include "arch/mips/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
 
@@ -102,28 +102,28 @@ FaultStat IntegerOverflowFault::_count;
 
 #if FULL_SYSTEM
 
-void MipsFault::invoke(ExecContext * xc)
+void MipsFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     countStat()++;
 
     // exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
+    if (setRestartAddress() || !tc->inPalMode())
+        tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
+                   tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
     }
 
-    xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
-    xc->setNextPC(xc->readPC() + sizeof(MachInst));
+    tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
+    tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 134fa2c4e..d8bf59cc1 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -47,7 +47,7 @@ class MipsFault : public FaultBase
     virtual bool setRestartAddress() {return true;}
   public:
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -114,7 +114,7 @@ class ArithmeticFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
index f577a1c94..056c8baff 100644
--- a/src/arch/mips/isa_traits.cc
+++ b/src/arch/mips/isa_traits.cc
@@ -40,7 +40,7 @@ using namespace std;
 
 
 void
-MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 {
     /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
     uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
@@ -53,7 +53,7 @@ MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
 }
 
 void
-MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
+MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
 {
     /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
     uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index e99bc7395..dc8b6758a 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -48,7 +48,7 @@
 class FastCPU;
 class FullCPU;
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 
 namespace LittleEndianGuest {};
 
@@ -131,14 +131,14 @@ namespace MipsISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
 
     const Addr MaxAddr = (Addr)-1;
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
     uint64_t fpConvert(double fp_val, ConvertType cvt_type);
     double roundFP(double val, int digits);
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index 1408dbac0..4a919ac27 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -33,7 +33,7 @@
 #include "arch/mips/isa_traits.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"
 
 #include "sim/process.hh"
@@ -45,9 +45,9 @@ using namespace MipsISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "mips");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
     return 0;
 }
 
@@ -64,18 +64,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
 /// different in practice from those used by Tru64 processes.
 static SyscallReturn
 sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 45: { // GSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(xc->getMemPort());
+          fpcr.copyOut(tc->getMemPort());
           return 0;
       }
 
@@ -91,17 +91,17 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
 /// Target sys_setsysinfo() handler.
 static SyscallReturn
 sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
-                   ExecContext *xc)
+                   ThreadContext *tc)
 {
-    unsigned op = xc->getSyscallArg(0);
-    // unsigned nbytes = xc->getSyscallArg(2);
+    unsigned op = tc->getSyscallArg(0);
+    // unsigned nbytes = tc->getSyscallArg(2);
 
     switch (op) {
 
       case 14: { // SSI_IEEE_FP_CONTROL
-          TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+          TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(xc->getMemPort());
+          fpcr.copyIn(tc->getMemPort());
           DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 13d8ac3a8..bd7aa394e 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -34,7 +34,7 @@
 #include "arch/mips/linux/process.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 3781a91f3..013aa01c7 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -40,7 +40,7 @@
 #include "sim/host.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 class Regfile;
 
 namespace MipsISA
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 2a0db38a4..dc82a3c26 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -37,7 +37,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 class Regfile;
 
 namespace MipsISA
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 72aa17424..f8aeab8cb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -36,7 +36,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 class Regfile;
 
 namespace MipsISA
@@ -57,14 +57,14 @@ namespace MipsISA
         int getInstAsid();
         int getDataAsid();
 
-        void copyMiscRegs(ExecContext *xc);
+        void copyMiscRegs(ThreadContext *tc);
 
         MiscReg readReg(int misc_reg)
         {
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
+        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
@@ -75,7 +75,7 @@ namespace MipsISA
         }
 
         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
-                               ExecContext *xc)
+                               ThreadContext *tc)
         {
             miscRegFile[misc_reg] = val; return NoFault;
         }
@@ -87,9 +87,9 @@ namespace MipsISA
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
       private:
-        MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
+        MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
 
-        Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
+        Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
 #endif
         friend class RegFile;
     };
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index e1b834568..af61e62cd 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -39,7 +39,7 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ExecContext;
+class ThreadContext;
 
 namespace MipsISA
 {
@@ -64,10 +64,10 @@ namespace MipsISA
         }
 
         MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ExecContext *xc)
+                Fault &fault, ThreadContext *tc)
         {
             fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
         }
 
         Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -76,9 +76,9 @@ namespace MipsISA
         }
 
         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc)
+                ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+            return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
@@ -189,12 +189,12 @@ namespace MipsISA
         }
     };
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
 #if FULL_SYSTEM
-    void copyIprs(ExecContext *src, ExecContext *dest);
+    void copyIprs(ThreadContext *src, ThreadContext *dest);
 #endif
 } // namespace MipsISA
 
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index 3516b1d19..38767cef7 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -34,13 +34,13 @@
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
-class ExecContext;
+class ThreadContext;
 class StackTrace;
 
 class ProcessInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
     int thread_info_size;
     int task_struct_size;
@@ -49,7 +49,7 @@ class ProcessInfo
     int name_off;
 
   public:
-    ProcessInfo(ExecContext *_xc);
+    ProcessInfo(ThreadContext *_tc);
 
     Addr task(Addr ksp) const;
     int pid(Addr ksp) const;
@@ -61,7 +61,7 @@ class StackTrace
   protected:
     typedef TheISA::MachInst MachInst;
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
     std::vector<Addr> stack;
 
   private:
@@ -70,21 +70,21 @@ class StackTrace
     bool decodeSave(MachInst inst, int &reg, int &disp);
     bool decodeStack(MachInst inst, int &disp);
 
-    void trace(ExecContext *xc, bool is_call);
+    void trace(ThreadContext *tc, bool is_call);
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
+    StackTrace(ThreadContext *tc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
     {
-        xc = 0;
+        tc = 0;
         stack.clear();
     }
 
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
+    bool valid() const { return tc != NULL; }
+    bool trace(ThreadContext *tc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -106,7 +106,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
@@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
     if (valid())
         clear();
 
-    trace(xc, !inst->isReturn());
+    trace(tc, !inst->isReturn());
     return true;
 }