mem: update stuff for changes to Packet and Request

3 files changed, 6 insertions, 5 deletions

diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index f0210c29b..8596308e2 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -43,7 +43,7 @@ output header {{
       protected:
 
         /// Memory request flags.  See mem_req_base.hh.
-        unsigned memAccessFlags;
+        Request::Flags memAccessFlags;
         /// Pointer to EAComp object.
         const StaticInstPtr eaCompPtr;
         /// Pointer to MemAcc object.
@@ -57,7 +57,7 @@ output header {{
                StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : MipsStaticInst(mnem, _machInst, __opClass),
-              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
+              eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
               disp(sext<16>(OFFSET))
         {
         }
@@ -70,7 +70,7 @@ output header {{
         const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
         const StaticInstPtr &memAccInst() const { return memAccPtr; }
 
-        unsigned memAccFlags() { return memAccessFlags; }
+        Request::Flags memAccFlags() { return memAccessFlags; }
     };
 
      /**
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 0405aa5b3..786a964d4 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -61,7 +61,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                         inst_flags)
 
     if mem_flags:
-        s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+        mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
+        s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');'
         iop.constructor += s
         memacc_iop.constructor += s
 
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 7c3b6aed5..e91da4eea 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -149,7 +149,7 @@ TLB::checkCacheability(RequestPtr &req)
   // or by the TLB entry
   if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
     // mark request as uncacheable
-    req->setFlags(req->getFlags() | UNCACHEABLE);
+      req->setFlags(Request::UNCACHEABLE);
   }
   return NoFault;
 }