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authorNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
committerNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
commita4c6f0d69eda5d23b12576080d532ddf768fbdbe (patch)
tree72863fc8729c977d15d1c60aeb8243407e964550 /src/arch/mips
parent7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 (diff)
downloadgem5-a4c6f0d69eda5d23b12576080d532ddf768fbdbe.tar.xz
Use PacketPtr everywhere
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
Diffstat (limited to 'src/arch/mips')
-rw-r--r--src/arch/mips/isa/formats/mem.isa10
-rw-r--r--src/arch/mips/isa/includes.isa20
2 files changed, 16 insertions, 14 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index d6b0c2938..e786cfbe2 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -162,7 +162,7 @@ def template InitiateAccDeclare {{
def template CompleteAccDeclare {{
- Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@@ -288,7 +288,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -412,7 +412,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -434,7 +434,7 @@ def template StoreCompleteAcc {{
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -509,7 +509,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 44926d772..274fdcaa1 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -38,23 +38,25 @@ output header {{
#include <iostream>
#include <iomanip>
-#include "cpu/static_inst.hh"
#include "arch/mips/isa_traits.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
}};
output decoder {{
+#include <cmath>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/isa_traits.hh"
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
-#include "arch/mips/faults.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
using namespace MipsISA;
}};