Merge zizzer:/bk/newmem

into  zeep.pool:/tmp/newmem

--HG--
extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572

3 files changed, 14 insertions, 14 deletions

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 3a8688797..b5d1df4fc 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -289,8 +289,8 @@ decode OPCODE_HI default Unknown::unknown() {
         0x0: decode RS_MSB {
             0x0: decode RS {
                 format CP0Control {
-                    0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
-                    0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
+                    0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }});
+                    0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }});
                 }
 
                 format MipsMT {
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 368925e00..53ee09512 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -215,22 +215,22 @@ namespace MipsISA
 
         void copyMiscRegs(ThreadContext *tc);
 
-        MiscReg readReg(int misc_reg)
+        MiscReg readRegNoEffect(int misc_reg)
         {
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc)
+        MiscReg readReg(int misc_reg, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
 
-        void setReg(int misc_reg, const MiscReg &val)
+        void setRegNoEffect(int misc_reg, const MiscReg &val)
         {
             miscRegFile[misc_reg] = val;
         }
 
-        void setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setReg(int misc_reg, const MiscReg &val,
                                ThreadContext *tc)
         {
             miscRegFile[misc_reg] = val;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 7b57b31f5..387fbd5c8 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -57,25 +57,25 @@ namespace MipsISA
             bzero(&miscRegFile, sizeof(miscRegFile));
         }
 
-        MiscReg readMiscReg(int miscReg)
+        MiscReg readMiscRegNoEffect(int miscReg)
         {
-            return miscRegFile.readReg(miscReg);
+            return miscRegFile.readRegNoEffect(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, tc);
+            return miscRegFile.readReg(miscReg, tc);
         }
 
-        void setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
         {
-            miscRegFile.setReg(miscReg, val);
+            miscRegFile.setRegNoEffect(miscReg, val);
         }
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setReg(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)