alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.

Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.

Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12 files changed, 72 insertions, 62 deletions

diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index 98da450d8..7431b94f5 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -33,7 +33,7 @@
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
-        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const;
 }};
 
 // Basic instruction class declaration template.
@@ -61,7 +61,8 @@ def template BasicConstructor {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 123468287..00600712c 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -80,7 +80,8 @@ output header {{
 
 // Basic instruction class execute method template.
 def template CP0Execute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
                 %(op_decl)s;
@@ -101,7 +102,8 @@ def template CP0Execute {{
 }};
 
 def template CP1Execute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
                 %(op_decl)s;
@@ -122,7 +124,8 @@ def template CP1Execute {{
 }};
 // Basic instruction class execute method template.
 def template ControlTLBExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
             %(op_decl)s;
@@ -173,15 +176,15 @@ output decoder {{
 }};
 
 output header {{
-        bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
+        bool isCoprocessorEnabled(ExecContext *xc, unsigned cop_num);
 
-        bool isMMUTLB(%(CPU_exec_context)s *xc);
+        bool isMMUTLB(ExecContext *xc);
 
 }};
 
 output exec {{
         bool
-        isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num)
+        isCoprocessorEnabled(ExecContext *xc, unsigned cop_num)
         {
             if (!FullSystem)
                 return true;
@@ -203,7 +206,7 @@ output exec {{
         }
 
         bool inline
-        isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc)
+        isCoprocessor0Enabled(ExecContext *xc)
         {
             if (FullSystem) {
                 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -219,7 +222,7 @@ output exec {{
         }
 
         bool
-        isMMUTLB(CPU_EXEC_CONTEXT *xc)
+        isMMUTLB(ExecContext *xc)
         {
             MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
             return FullSystem && (Config & 0x380) == 0x80;
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2a946ed9d..78fb93063 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -64,7 +64,8 @@ output header {{
 
 // Dsp instruction class execute method template.
 def template DspExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
@@ -97,7 +98,8 @@ def template DspExecute {{
 
 // DspHiLo instruction class execute method template.
 def template DspHiLoExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
@@ -136,9 +138,9 @@ def template DspHiLoExecute {{
 }};
 
 output header {{
-    bool isDspEnabled(%(CPU_exec_context)s *xc);
+    bool isDspEnabled(ExecContext *xc);
 
-    bool isDspPresent(%(CPU_exec_context)s *xc);
+    bool isDspPresent(ExecContext *xc);
 }};
 
 //Outputs to decoder.cc
@@ -147,7 +149,7 @@ output decoder {{
 
 output exec {{
     bool
-    isDspEnabled(CPU_EXEC_CONTEXT *xc)
+    isDspEnabled(ExecContext *xc)
     {
         return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
     }
@@ -155,7 +157,7 @@ output exec {{
 
 output exec {{
     bool
-    isDspPresent(CPU_EXEC_CONTEXT *xc)
+    isDspPresent(ExecContext *xc)
     {
         return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
     }
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index c0dff477b..eb5e5765a 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -87,12 +87,12 @@ output decoder {{
 }};
 
 output header {{
-        void fpResetCauseBits(%(CPU_exec_context)s *cpu);
+        void fpResetCauseBits(ExecContext *cpu);
 
 }};
 
 output exec {{
-        inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
+        inline Fault checkFpEnableFault(ExecContext *xc)
         {
             //@TODO: Implement correct CP0 checks to see if the CP1
             // unit is enable or not
@@ -105,7 +105,7 @@ output exec {{
         //If any operand is Nan return the appropriate QNaN
         template <class T>
         bool
-        fpNanOperands(FPOp *inst, CPU_EXEC_CONTEXT *xc, const T &src_type,
+        fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
                       Trace::InstRecord *traceData)
         {
             uint64_t mips_nan = 0;
@@ -126,7 +126,7 @@ output exec {{
 
         template <class T>
         bool
-        fpInvalidOp(FPOp *inst, CPU_EXEC_CONTEXT *cpu, const T dest_val,
+        fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
                     Trace::InstRecord *traceData)
         {
             uint64_t mips_nan = 0;
@@ -156,7 +156,7 @@ output exec {{
         }
 
         void
-        fpResetCauseBits(CPU_EXEC_CONTEXT *cpu)
+        fpResetCauseBits(ExecContext *cpu)
         {
             //Read FCSR from FloatRegFile
             uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
@@ -170,7 +170,8 @@ output exec {{
 }};
 
 def template FloatingPointExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index c21c1255b..9f43ac275 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -133,7 +133,8 @@ output header {{
 
 // HiLo instruction class execute method template.
 def template HiLoExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
@@ -152,7 +153,8 @@ def template HiLoExecute {{
 
 // HiLoRsSel instruction class execute method template.
 def template HiLoRsSelExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
@@ -178,7 +180,8 @@ def template HiLoRsSelExecute {{
 
 // HiLoRdSel instruction class execute method template.
 def template HiLoRdSelExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
 
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 052ead82c..9e5f538e6 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -97,7 +97,7 @@ output decoder {{
 }};
 
 output header {{
-    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
+    uint64_t getMemData(ExecContext *xc, Packet *packet);
 
 }};
 
@@ -105,7 +105,7 @@ output exec {{
     /** return data in cases where there the size of data is only
         known in the packet
     */
-    uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) {
+    uint64_t getMemData(ExecContext *xc, Packet *packet) {
         switch (packet->getSize())
         {
           case 1:
@@ -153,16 +153,16 @@ def template LoadStoreDeclare {{
 }};
 
 def template EACompDeclare {{
-    Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault eaComp(ExecContext *, Trace::InstRecord *) const;
 }};
 
 def template InitiateAccDeclare {{
-    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
 }};
 
 
 def template CompleteAccDeclare {{
-    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
 }};
 
 def template LoadStoreConstructor {{
@@ -176,8 +176,7 @@ def template LoadStoreConstructor {{
 
 def template EACompExecute {{
     Fault
-    %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
-                                   Trace::InstRecord *traceData) const
+    %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
     {
         Addr EA;
         Fault fault = NoFault;
@@ -203,7 +202,7 @@ def template EACompExecute {{
 }};
 
 def template LoadExecute {{
-    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -235,7 +234,7 @@ def template LoadExecute {{
 
 
 def template LoadInitiateAcc {{
-    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::initiateAcc(ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -261,8 +260,7 @@ def template LoadInitiateAcc {{
 }};
 
 def template LoadCompleteAcc {{
-    Fault %(class_name)s::completeAcc(Packet *pkt,
-                                      CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         Fault fault = NoFault;
@@ -292,7 +290,7 @@ def template LoadCompleteAcc {{
 }};
 
 def template StoreExecute {{
-    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -326,7 +324,7 @@ def template StoreExecute {{
 
 
 def template StoreFPExecute {{
-    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -361,7 +359,7 @@ def template StoreFPExecute {{
 }};
 
 def template StoreCondExecute {{
-    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -395,7 +393,7 @@ def template StoreCondExecute {{
 }};
 
 def template StoreInitiateAcc {{
-    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::initiateAcc(ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         Addr EA;
@@ -422,7 +420,7 @@ def template StoreInitiateAcc {{
 
 def template StoreCompleteAcc {{
     Fault %(class_name)s::completeAcc(Packet *pkt,
-                                      CPU_EXEC_CONTEXT *xc,
+                                      ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         return NoFault;
@@ -431,7 +429,7 @@ def template StoreCompleteAcc {{
 
 def template StoreCondCompleteAcc {{
     Fault %(class_name)s::completeAcc(Packet *pkt,
-                                      CPU_EXEC_CONTEXT *xc,
+                                      ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         Fault fault = NoFault;
@@ -454,7 +452,7 @@ def template StoreCondCompleteAcc {{
 }};
 
 def template MiscExecute {{
-    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::execute(ExecContext *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA M5_VAR_USED = 0;
@@ -474,7 +472,7 @@ def template MiscExecute {{
 }};
 
 def template MiscInitiateAcc {{
-    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::initiateAcc(ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         panic("Misc instruction does not support split access method!");
@@ -484,8 +482,7 @@ def template MiscInitiateAcc {{
 
 
 def template MiscCompleteAcc {{
-    Fault %(class_name)s::completeAcc(Packet *pkt,
-                                      CPU_EXEC_CONTEXT *xc,
+    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
         panic("Misc instruction does not support split access method!");
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index b34773ef5..b9ee07010 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -85,18 +85,18 @@ output decoder {{
 }};
 
 output header {{
-   void getThrRegExValues(%(CPU_exec_context)s *xc,
+   void getThrRegExValues(ExecContext *xc,
                           MipsISA::VPEConf0Reg &vpe_conf0,
                           MipsISA::TCBindReg &tc_bind_mt,
                           MipsISA::TCBindReg &tc_bind,
                           MipsISA::VPEControlReg &vpe_control,
                           MipsISA::MVPConf0Reg &mvp_conf0);
 
-   void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3);
+   void getMTExValues(ExecContext *xc, MipsISA::Config3Reg &config3);
 }};
 
 output exec {{
-    void getThrRegExValues(CPU_EXEC_CONTEXT *xc,
+    void getThrRegExValues(ExecContext *xc,
             VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
             TCBindReg &tc_bind, VPEControlReg &vpe_control,
             MVPConf0Reg &mvp_conf0)
@@ -109,14 +109,15 @@ output exec {{
         mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
     }
 
-    void getMTExValues(CPU_EXEC_CONTEXT *xc, Config3Reg &config3)
+    void getMTExValues(ExecContext *xc, Config3Reg &config3)
     {
         config3 = xc->readMiscReg(MISCREG_CONFIG3);
     }
 }};
 
 def template ThreadRegisterExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
             int64_t data M5_VAR_USED;
@@ -154,7 +155,8 @@ def template ThreadRegisterExecute {{
 }};
 
 def template MTExecute{{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
                 %(op_decl)s;
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 5964b0f0a..17c653f14 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -82,7 +82,7 @@ output decoder {{
 
 output exec {{
     Fault
-    Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const
+    Nop::execute(ExecContext *, Trace::InstRecord *) const
     {
         return NoFault;
     }
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index bd27a347c..4ec1d267e 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -58,7 +58,8 @@ output decoder {{
 }};
 
 def template TlbOpExecute {{
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 //Write the resulting state to the execution context
                 %(op_wb)s;
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 796cb5928..5133899ea 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -81,7 +81,8 @@ output decoder {{
 
 def template TrapExecute {{
         //Edit This Template When Traps Are Implemented
-        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(
+            ExecContext *xc, Trace::InstRecord *traceData) const
         {
                 //Write the resulting state to the execution context
                 %(op_wb)s;
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index a51865584..6f573b667 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -180,7 +180,7 @@ output decoder {{
 
 output exec {{
     Fault
-    FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
+    FailUnimplemented::execute(ExecContext *xc,
                                Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unimplemented instruction '%s' "
@@ -190,7 +190,7 @@ output exec {{
     }
 
     Fault
-    CP0Unimplemented::execute(CPU_EXEC_CONTEXT *xc,
+    CP0Unimplemented::execute(ExecContext *xc,
                                Trace::InstRecord *traceData) const
     {
         if (FullSystem) {
@@ -207,7 +207,7 @@ output exec {{
     }
 
     Fault
-    CP1Unimplemented::execute(CPU_EXEC_CONTEXT *xc,
+    CP1Unimplemented::execute(ExecContext *xc,
                                Trace::InstRecord *traceData) const
     {
         if (FullSystem) {
@@ -224,7 +224,7 @@ output exec {{
     }
 
     Fault
-    CP2Unimplemented::execute(CPU_EXEC_CONTEXT *xc,
+    CP2Unimplemented::execute(ExecContext *xc,
                                Trace::InstRecord *traceData) const
     {
         if (FullSystem) {
@@ -241,7 +241,7 @@ output exec {{
     }
 
     Fault
-    WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
+    WarnUnimplemented::execute(ExecContext *xc,
                                Trace::InstRecord *traceData) const
     {
         if (!warned) {
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index fd6c9ea18..fb29eea4b 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -69,8 +69,7 @@ output decoder {{
 
 output exec {{
     Fault
-    Unknown::execute(CPU_EXEC_CONTEXT *xc,
-                     Trace::InstRecord *traceData) const
+    Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
     {
         return std::make_shared<ReservedInstructionFault>();
     }