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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-20 16:24:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-20 16:24:40 -0500 |
| commit | 672d6a4b98165952e0afa0057f851f150bc657ec (patch) | |
| tree | 4bd03e87c875477d172910ee1a0a838111949d83 /src/arch/mips | |
| parent | 89850d6370b29272788cb73165341ced68e3bd53 (diff) | |
| download | gem5-672d6a4b98165952e0afa0057f851f150bc657ec.tar.xz | |
Style: Replace some tabs with spaces.
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/SConscript | 6 | ||||
| -rw-r--r-- | src/arch/mips/isa/bitfields.isa | 22 | ||||
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 4 |
3 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index ffc1f18eb..9e0275de7 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -44,15 +44,15 @@ if env['TARGET_ISA'] == 'mips': TraceFlag('MipsPRA') if env['FULL_SYSTEM']: - SimObject('MipsSystem.py') - SimObject('MipsInterrupts.py') + SimObject('MipsSystem.py') + SimObject('MipsInterrupts.py') Source('idle_event.cc') Source('mips_core_specific.cc') Source('vtophys.cc') Source('system.cc') Source('stacktrace.cc') Source('linux/system.cc') - Source('interrupts.cc') + Source('interrupts.cc') Source('bare_iron/system.cc') else: Source('process.cc') diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa index 85d2d96da..d2d119cac 100644 --- a/src/arch/mips/isa/bitfields.isa +++ b/src/arch/mips/isa/bitfields.isa @@ -46,27 +46,27 @@ def bitfield FUNCTION < 5: 0>; def bitfield FUNCTION_HI < 5: 3>; def bitfield FUNCTION_LO < 2: 0>; -def bitfield RS <25:21>; +def bitfield RS <25:21>; def bitfield RS_MSB <25:25>; def bitfield RS_HI <25:24>; def bitfield RS_LO <23:21>; def bitfield RS_SRL <25:22>; def bitfield RS_RT <25:16>; -def bitfield RT <20:16>; +def bitfield RT <20:16>; def bitfield RT_HI <20:19>; def bitfield RT_LO <18:16>; def bitfield RT_RD <20:11>; -def bitfield RD <15:11>; +def bitfield RD <15:11>; -def bitfield INTIMM <15: 0>; +def bitfield INTIMM <15: 0>; def bitfield RS_RT_INTIMM <25: 0>; // Floating-point operate format def bitfield FMT <25:21>; def bitfield FR <25:21>; -def bitfield FT <20:16>; -def bitfield FS <15:11>; -def bitfield FD <10:6>; +def bitfield FT <20:16>; +def bitfield FS <15:11>; +def bitfield FD <10:6>; def bitfield ND <17:17>; def bitfield TF <16:16>; @@ -90,15 +90,15 @@ def bitfield SC < 5: 5>; def bitfield OFFSET <15: 0>; // displacement // Jmp format -def bitfield JMPTARG <25: 0>; -def bitfield HINT <10: 6>; +def bitfield JMPTARG <25: 0>; +def bitfield HINT <10: 6>; def bitfield SYSCALLCODE <25: 6>; def bitfield TRAPCODE <15:13>; // EXT/INS instructions -def bitfield MSB <15:11>; -def bitfield LSB <10: 6>; +def bitfield MSB <15:11>; +def bitfield LSB <10: 6>; // M5 instructions def bitfield M5FUNC <7:0>; diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 8a8033a00..173fa89df 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -1131,7 +1131,7 @@ decode OPCODE_HI default Unknown::unknown() { UnorderedFalse); 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, UnorderedTrue); - 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, + 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, UnorderedFalse); 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, UnorderedTrue); @@ -1252,7 +1252,7 @@ decode OPCODE_HI default Unknown::unknown() { UnorderedFalse); 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, UnorderedTrue); - 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, + 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, UnorderedFalse); 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, UnorderedTrue); |