Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world

--HG--
extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10

5 files changed, 72 insertions, 50 deletions

diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index b2735d0e7..d06a0e7dd 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -39,19 +39,19 @@ class MipsTLB(SimObject):
     size = Param.Int("TLB size")
 
 class MipsDTB(MipsTLB):
-    type = 'DTB'
+    type = 'MipsDTB'
     cxx_namespace = 'MipsISA'
     cxx_class = 'DTB'
     size = 64
 
 class MipsITB(MipsTLB):
-    type = 'ITB'
+    type = 'MipsITB'
     cxx_namespace = 'MipsISA'
     cxx_class = 'ITB'
     size = 64
 
 class MipsUTB(MipsTLB):
-    type = 'UTB'
+    type = 'MipsUTB'
     cxx_namespace = 'MipsISA'
     cxx_class = 'UTB'
     size = 64
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 8398ae405..3e1cb69c9 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -57,7 +57,7 @@ FaultName AlignmentFault::_name = "Alignment";
 FaultVect AlignmentFault::_vect = 0x0301;
 FaultStat AlignmentFault::_count;
 
-FaultName ResetFault::_name = "reset";
+FaultName ResetFault::_name = "Reset Fault";
 #if  FULL_SYSTEM
 FaultVect ResetFault::_vect = 0xBFC00000;
 #else
@@ -78,15 +78,15 @@ FaultName SystemCallFault::_name = "Syscall";
 FaultVect SystemCallFault::_vect = 0x0180;
 FaultStat SystemCallFault::_count;
 
-FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
+FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
 FaultVect CoprocessorUnusableFault::_vect = 0x180;
 FaultStat CoprocessorUnusableFault::_count;
 
-FaultName ReservedInstructionFault::_name = "Reserved Instruction";
+FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
 FaultVect ReservedInstructionFault::_vect = 0x0180;
 FaultStat ReservedInstructionFault::_count;
 
-FaultName ThreadFault::_name = "thread";
+FaultName ThreadFault::_name = "Thread Fault";
 FaultVect ThreadFault::_vect = 0x00F1;
 FaultStat ThreadFault::_count;
 
@@ -459,12 +459,17 @@ void InterruptFault::invoke(ThreadContext *tc)
 
 void ResetFault::invoke(ThreadContext *tc)
 {
+#if FULL_SYSTEM
   DPRINTF(MipsPRA,"%s encountered.\n", name());
   /* All reset activity must be invoked from here */
   tc->setPC(vect());
   tc->setNextPC(vect()+sizeof(MachInst));
   tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
   DPRINTF(MipsPRA,"(%x)  -  ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
+#endif
+
+  // Set Coprocessor 1 (Floating Point) To Usable
+  tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
 }
 
 void ReservedInstructionFault::invoke(ThreadContext *tc)
@@ -509,7 +514,7 @@ void CoprocessorUnusableFault::invoke(ThreadContext *tc)
 
   //      warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause));
 #else
-    panic("%s encountered.\n", name());
+    warn("%s (CP%d) encountered.\n", name(), coProcID);
 #endif
 }
 
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 84c944586..75157ab92 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -1,38 +1,32 @@
 /*
- * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
- *
- * Authors: Gabe M. Black
- *          Korey L. Sewell
+ * Authors: Gabe Black
+ *          Korey Sewell
  *          Jaidev Patwardhan
  */
 
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 4593aa52b..1671b9ad7 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -183,22 +183,22 @@ output decoder {{
 output exec {{
         bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
         {
+#if !FULL_SYSTEM
+            return true;
+#else
           MiscReg Stat = xc->readMiscReg(MipsISA::Status);
           switch(cop_num)
             {
             case 0:
               {
-#if FULL_SYSTEM
-              MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
-              if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
-                 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
-                 && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
-                // Unable to use Status_CU0, etc directly, using bitfields & masks
-                  return false;
-              }
-#else
-              //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
-#endif
+                  MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+                  if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
+                     && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+                     && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
+                      // Unable to use Status_CU0, etc directly, using bitfields & masks
+                      return false;
+                  }
+
               }
               break;
             case 1:
@@ -217,6 +217,7 @@ output exec {{
               break;
             }
             return true;
+#endif
         }
         bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
         {
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 15f4b762b..526292603 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -47,6 +47,8 @@
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "sim/process.hh"
+#include "mem/page_table.hh"
 #include "params/MipsDTB.hh"
 #include "params/MipsITB.hh"
 #include "params/MipsTLB.hh"
@@ -314,6 +316,15 @@ TLB::regStats()
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
+#if !FULL_SYSTEM
+    Process * p = tc->getProcessPtr();
+
+    Fault fault = p->pTable->translate(req);
+    if(fault != NoFault)
+        return fault;
+
+    return NoFault;
+#else
   if(MipsISA::IsKSeg0(req->getVaddr()))
     {
       // Address will not be translated through TLB, set response, and go!
@@ -416,11 +427,21 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
         }
     }
   return checkCacheability(req);
+#endif
 }
 
 Fault
 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
+#if !FULL_SYSTEM
+    Process * p = tc->getProcessPtr();
+
+    Fault fault = p->pTable->translate(req);
+    if(fault != NoFault)
+        return fault;
+
+    return NoFault;
+#else
   if(MipsISA::IsKSeg0(req->getVaddr()))
     {
       // Address will not be translated through TLB, set response, and go!
@@ -544,6 +565,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
         }
     }
     return checkCacheability(req);
+#endif
 }
 
 ///////////////////////////////////////////////////////////////////////