arm: remote GDB: rationalize structure of register offsets

Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays.  The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question.  This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).

With this patch I propose a simpler mechanism for expressing the
register set structure.  In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation.  The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.

This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.

Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>

2 files changed, 63 insertions, 74 deletions

diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index a7bde8ba6..68d8eaa57 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
  * All rights reserved
@@ -41,6 +42,7 @@
  * Authors: Nathan Binkert
  *          William Wang
  *          Deyuan Guo
+ *          Boris Shingarov
  */
 
 /*
@@ -149,7 +151,7 @@ using namespace std;
 using namespace MipsISA;
 
 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
-    : BaseRemoteGDB(_system, tc, GdbNumRegs * sizeof(uint32_t))
+    : BaseRemoteGDB(_system, tc)
 {
 }
 
@@ -168,70 +170,41 @@ RemoteGDB::acc(Addr va, size_t len)
         return context->getProcessPtr()->pTable->lookup(va, entry);
 }
 
-/*
- * Translate the kernel debugger register format into the GDB register
- * format.
- */
 void
-RemoteGDB::getregs()
+RemoteGDB::MipsGdbRegCache::getRegs(ThreadContext *context)
 {
     DPRINTF(GDBAcc, "getregs in remotegdb \n");
-    memset(gdbregs.regs, 0, gdbregs.bytes());
 
-    // MIPS registers are 32 bits wide, gdb registers are 64 bits wide
-    // two MIPS registers are packed into one gdb register (little endian)
-
-    // INTREG: R0~R31
-    for (int i = 0; i < GdbIntArchRegs; i++)
-        gdbregs.regs32[i] = context->readIntReg(i);
-    // SR, LO, HI, BADVADDR, CAUSE, PC
-    gdbregs.regs32[GdbIntArchRegs + 0] =
-        context->readMiscRegNoEffect(MISCREG_STATUS);
-    gdbregs.regs32[GdbIntArchRegs + 1] = context->readIntReg(INTREG_LO);
-    gdbregs.regs32[GdbIntArchRegs + 2] = context->readIntReg(INTREG_HI);
-    gdbregs.regs32[GdbIntArchRegs + 3] =
-        context->readMiscRegNoEffect(MISCREG_BADVADDR);
-    gdbregs.regs32[GdbIntArchRegs + 4] =
-        context->readMiscRegNoEffect(MISCREG_CAUSE);
-    gdbregs.regs32[GdbIntArchRegs + 5] = context->pcState().pc();
-    // FLOATREG: F0~F31
-    for (int i = 0; i < GdbFloatArchRegs; i++)
-        gdbregs.regs32[GdbIntRegs + i] = context->readFloatRegBits(i);
-    // FCR, FIR
-    gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 0] =
-        context->readFloatRegBits(FLOATREG_FCCR);
-    gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 1] =
-        context->readFloatRegBits(FLOATREG_FIR);
+    for (int i = 0; i < 32; i++) r.gpr[i] = context->readIntReg(i);
+    r.sr = context->readMiscRegNoEffect(MISCREG_STATUS);
+    r.lo = context->readIntReg(INTREG_LO);
+    r.hi = context->readIntReg(INTREG_HI);
+    r.badvaddr = context->readMiscRegNoEffect(MISCREG_BADVADDR);
+    r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE);
+    r.pc = context->pcState().pc();
+    for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatRegBits(i);
+    r.fsr = context->readFloatRegBits(FLOATREG_FCCR);
+    r.fir = context->readFloatRegBits(FLOATREG_FIR);
 }
 
-/*
- * Translate the GDB register format into the kernel debugger register
- * format.
- */
 void
-RemoteGDB::setregs()
+RemoteGDB::MipsGdbRegCache::setRegs(ThreadContext *context) const
 {
     DPRINTF(GDBAcc, "setregs in remotegdb \n");
 
-    // INTREG: R0~R31
-    for (int i = 1; i < GdbIntArchRegs; i++)
-        context->setIntReg(i, gdbregs.regs32[i]);
-    // SR, LO, HI, BADVADDR, CAUSE, PC
-    context->setMiscRegNoEffect(MISCREG_STATUS,
-        gdbregs.regs32[GdbIntArchRegs + 0]);
-    context->setIntReg(INTREG_LO, gdbregs.regs32[GdbIntArchRegs + 1]);
-    context->setIntReg(INTREG_HI, gdbregs.regs32[GdbIntArchRegs + 2]);
-    context->setMiscRegNoEffect(MISCREG_BADVADDR,
-        gdbregs.regs32[GdbIntArchRegs + 3]);
-    context->setMiscRegNoEffect(MISCREG_CAUSE,
-        gdbregs.regs32[GdbIntArchRegs + 4]);
-    context->pcState(gdbregs.regs32[GdbIntArchRegs + 5]);
-    // FLOATREG: F0~F31
-    for (int i = 0; i < GdbFloatArchRegs; i++)
-        context->setFloatRegBits(i, gdbregs.regs32[GdbIntRegs + i]);
-    // FCR, FIR
-    context->setFloatRegBits(FLOATREG_FCCR,
-        gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 0]);
-    context->setFloatRegBits(FLOATREG_FIR,
-        gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 1]);
+    for (int i = 1; i < 32; i++) context->setIntReg(i, r.gpr[i]);
+    context->setMiscRegNoEffect(MISCREG_STATUS, r.sr);
+    context->setIntReg(INTREG_LO, r.lo);
+    context->setIntReg(INTREG_HI, r.hi);
+    context->setMiscRegNoEffect(MISCREG_BADVADDR, r.badvaddr);
+    context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause);
+    context->pcState(r.pc);
+    for (int i = 0; i < 32; i++) context->setFloatRegBits(i, r.fpr[i]);
+    context->setFloatRegBits(FLOATREG_FCCR, r.fsr);
+    context->setFloatRegBits(FLOATREG_FIR, r.fir);
+}
+
+RemoteGDB::BaseGdbRegCache*
+RemoteGDB::gdbRegs() {
+    return new MipsGdbRegCache(this);
 }
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 8d113eb99..fd006e0b6 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2007 The Regents of The University of Michigan
  * All rights reserved.
@@ -27,6 +28,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Nathan Binkert
+ *          Boris Shingarov
  */
 
 #ifndef __ARCH_MIPS_REMOTE_GDB_HH__
@@ -42,27 +44,41 @@ class ThreadContext;
 namespace MipsISA
 {
 
-    // The number of special regs depends on gdb.
-    const int GdbIntArchRegs = NumIntArchRegs;
-    const int GdbIntSpecialRegs = 6;
-    const int GdbFloatArchRegs = NumFloatArchRegs;
-    const int GdbFloatSpecialRegs = 2;
-
-    const int GdbIntRegs = GdbIntArchRegs + GdbIntSpecialRegs;
-    const int GdbFloatRegs = GdbFloatArchRegs + GdbFloatSpecialRegs;
-    const int GdbNumRegs = GdbIntRegs + GdbFloatRegs;
+class RemoteGDB : public BaseRemoteGDB
+{
+  protected:
+    bool acc(Addr addr, size_t len);
 
-    class RemoteGDB : public BaseRemoteGDB
+    class MipsGdbRegCache : public BaseGdbRegCache
     {
+      using BaseGdbRegCache::BaseGdbRegCache;
+      private:
+        struct {
+            uint32_t gpr[32];
+            uint32_t sr;
+            uint32_t lo;
+            uint32_t hi;
+            uint32_t badvaddr;
+            uint32_t cause;
+            uint32_t pc;
+            uint32_t fpr[32];
+            uint32_t fsr;
+            uint32_t fir;
+        } r;
       public:
-        RemoteGDB(System *_system, ThreadContext *tc);
+        char *data() const { return (char *)&r; }
+        size_t size() const { return sizeof(r); }
+        void getRegs(ThreadContext*);
+        void setRegs(ThreadContext*) const;
+        const std::string name() const { return gdb->name() + ".MipsGdbRegCache"; }
+    };
 
-      protected:
-        bool acc(Addr addr, size_t len);
 
-        void getregs();
-        void setregs();
-    };
-}
+  public:
+    RemoteGDB(System *_system, ThreadContext *tc);
+    BaseGdbRegCache *gdbRegs();
+};
+
+} // namespace MipsISA
 
 #endif /* __ARCH_MIPS_REMOTE_GDB_H__ */