Clock: Add a Cycles wrapper class and use where applicable

This patch addresses the comments and feedback on the preceding patch
that reworks the clocks and now more clearly shows where cycles
(relative cycle counts) are used to express time.

Instead of bumping the existing patch I chose to make this a separate
patch, merely to try and focus the discussion around a smaller set of
changes. The two patches will be pushed together though.

This changes done as part of this patch are mostly following directly
from the introduction of the wrapper class, and change enough code to
make things compile and run again. There are definitely more places
where int/uint/Tick is still used to represent cycles, and it will
take some time to chase them all down. Similarly, a lot of parameters
should be changed from Param.Tick and Param.Unsigned to
Param.Cycles.

In addition, the use of curTick is questionable as there should not be
an absolute cycle. Potential solutions can be built on top of this
patch. There is a similar situation in the o3 CPU where
lastRunningCycle is currently counting in Cycles, and is still an
absolute time. More discussion to be had in other words.

An additional change that would be appropriate in the future is to
perform a similar wrapping of Tick and probably also introduce a
Ticks class along with suitable operators for all these classes.

5 files changed, 11 insertions, 11 deletions

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6a525ed3a..f6de102cd 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -482,7 +482,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
 
     miscRegFile[misc_reg][reg_sel] = cp0_val;
 
-    scheduleCP0Update(tc->getCpuPtr(), 1);
+    scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
 }
 
 /**
@@ -511,14 +511,14 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
 }
 
 void
-ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
 {
     if (!cp0Updated) {
         cp0Updated = true;
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
+        cpu->schedule(cp0_event, cpu->clockEdge(delay));
     }
 }
 
@@ -573,9 +573,9 @@ ISA::CP0Event::description() const
 }
 
 void
-ISA::CP0Event::scheduleEvent(int delay)
+ISA::CP0Event::scheduleEvent(Cycles delay)
 {
-    cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
+    cpu->reschedule(this, cpu->clockEdge(delay), true);
 }
 
 void
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 720c7725e..a313b4382 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -136,14 +136,14 @@ namespace MipsISA
             const char *description() const;
 
             /** Schedule This Event */
-            void scheduleEvent(int delay);
+            void scheduleEvent(Cycles delay);
 
             /** Unschedule This Event */
             void unscheduleEvent();
         };
 
         // Schedule a CP0 Update Event
-        void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
+        void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
 
         // If any changes have been made, then check the state for changes
         // and if necessary alert the CPU
diff --git a/src/arch/mips/mmapped_ipr.hh b/src/arch/mips/mmapped_ipr.hh
index 14d6e3f42..4c84d05f2 100644
--- a/src/arch/mips/mmapped_ipr.hh
+++ b/src/arch/mips/mmapped_ipr.hh
@@ -45,13 +45,13 @@ class ThreadContext;
 namespace MipsISA
 {
 
-inline Tick
+inline Cycles
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
     panic("No implementation for handleIprRead in MIPS\n");
 }
 
-inline Tick
+inline Cycles
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
     panic("No implementation for handleIprWrite in MIPS\n");
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index f163d3240..02e98a170 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -96,7 +96,7 @@ restoreThread(TC *tc)
 
         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
         tc->pcState(restartPC);
-        tc->activate(0);
+        tc->activate(Cycles(0));
 
         warn("%i: Restoring thread %i in %s @ PC %x",
                 curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 65432b4ea..f84819756 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -231,7 +231,7 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0/*tc->threadId()*/);
+    tc->activate(Cycles(0));
 }
 
 void