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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-15 03:10:41 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-15 03:10:41 -0500 |
| commit | 789153dff64edcf046d800f231dffa6d66004ed5 (patch) | |
| tree | 23af9c76854b19aff31c27173de9897729b6ab9a /src/arch/mips | |
| parent | 375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8 (diff) | |
| download | gem5-789153dff64edcf046d800f231dffa6d66004ed5.tar.xz | |
Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/faults.cc | 2 | ||||
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 3e1cb69c9..b2778dcd0 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -196,7 +196,7 @@ void MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode) // Move ESS to CSS replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS); tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs); - tc->setShadowSet(ESS); + //tc->setShadowSet(ESS); } // set EXL bit (don't care if it is already set!) diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index eb1b0390a..9a2641138 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -652,7 +652,7 @@ decode OPCODE_HI default Unknown::unknown() { Status_EXL = 0; if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){ SRSCtl_CSS = SRSCtl_PSS; - xc->setShadowSet(SRSCtl_PSS); + //xc->setShadowSet(SRSCtl_PSS); } } LLFlag = 0; @@ -2086,7 +2086,7 @@ decode OPCODE_HI default Unknown::unknown() { format CP0Control { 0x7: cache({{ Addr CacheEA = Rs.uw + OFFSET; - fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); + //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); }}); } } |