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authorAli Saidi <saidi@eecs.umich.edu>2007-08-01 17:05:03 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-01 17:05:03 -0400
commit84cd78e96f892f52a715cfe10d9405987f5e9ba1 (patch)
treec05182e8f40fcbefbd1e26d16006ab4c1674a1b4 /src/arch/mips
parentfae60c164e284864cfabea515db6ba28d601b71d (diff)
parent239d124e8339b254495df45df89fc249ae217d73 (diff)
downloadgem5-84cd78e96f892f52a715cfe10d9405987f5e9ba1.tar.xz
Merge Gabe and my changes to arch/mips/utility.hh
--HG-- extra : convert_revision : d5a9d74ee6edf71524ba5c03fb7f054cf9722213
Diffstat (limited to 'src/arch/mips')
-rw-r--r--src/arch/mips/SConscript3
-rw-r--r--src/arch/mips/isa/decoder.isa3
-rw-r--r--src/arch/mips/isa/includes.isa1
-rw-r--r--src/arch/mips/isa_traits.cc100
-rwxr-xr-xsrc/arch/mips/mt_constants.hh1
-rwxr-xr-xsrc/arch/mips/regfile/misc_regfile.cc8
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh11
-rw-r--r--src/arch/mips/regfile/regfile.hh8
-rw-r--r--src/arch/mips/utility.hh2
9 files changed, 19 insertions, 118 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index de209348a..658710389 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,8 +34,9 @@ Import('*')
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
- Source('isa_traits.cc')
+ Source('regfile/int_regfile.cc')
Source('regfile/misc_regfile.cc')
+ Source('regfile/regfile.cc')
Source('utility.cc')
Source('dsp.cc')
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e55d2e070..40ea223f6 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
0x4: syscall({{ xc->syscall(R2); }},
- IsSerializeAfter, IsNonSpeculative);
+ IsSerializeAfter, IsNonSpeculative,
+ IsSyscall);
0x7: sync({{ ; }}, IsMemBarrier);
}
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 0e0cf44eb..0ce807a24 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -72,6 +72,7 @@ output exec {{
#include "arch/mips/dsp.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/dt_constants.hh"
+#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include <math.h>
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
deleted file mode 100644
index 0c84ce2b2..000000000
--- a/src/arch/mips/isa_traits.cc
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Korey Sewell
- */
-
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/regfile/regfile.hh"
-#include "sim/serialize.hh"
-#include "base/bitfield.hh"
-
-using namespace MipsISA;
-using namespace std;
-
-void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
-{
- panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-IntRegFile::serialize(std::ostream &os)
-{
- SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
- UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-RegFile::serialize(std::ostream &os)
-{
- intRegFile.serialize(os);
- //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
- //SERIALZE_ARRAY(miscRegFile);
- //SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.lock_flag);
- //SERIALIZE_SCALAR(miscRegs.lock_addr);
- SERIALIZE_SCALAR(pc);
- SERIALIZE_SCALAR(npc);
- SERIALIZE_SCALAR(nnpc);
-}
-
-
-void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
- intRegFile.unserialize(cp, section);
- //UNSERIALIZE_ARRAY(floatRegFile);
- //UNSERIALZE_ARRAY(miscRegFile);
- //UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
- //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
- UNSERIALIZE_SCALAR(pc);
- UNSERIALIZE_SCALAR(npc);
- UNSERIALIZE_SCALAR(nnpc);
-
-}
-
-
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index 0f6978433..57306d237 100755
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -31,7 +31,6 @@
#ifndef __ARCH_MIPS_MT_CONSTANTS_HH__
#define __ARCH_MIPS_MT_CONSTANTS_HH__
-#include "arch/mips/types.hh"
//#include "config/full_system.hh"
namespace MipsISA
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index c97d93cf9..8f8899e92 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -30,13 +30,13 @@
#include "base/bitfield.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
-#include "arch/mips/mt_constants.hh"
#include "arch/mips/faults.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
-#include "cpu/thread_context.hh"
#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
+#include "cpu/thread_context.hh"
//#include "cpu/mixie/cpu.hh"
using namespace std;
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 54b086a8b..0846378bb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -33,14 +33,12 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
-#include "base/bitfield.hh"
-#include "cpu/base.hh"
+#include "sim/eventq.hh"
#include "sim/faults.hh"
#include <queue>
class ThreadContext;
+class BaseCPU;
namespace MipsISA
{
@@ -76,7 +74,10 @@ namespace MipsISA
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc);
+ void copyMiscRegs(ThreadContext *tc)
+ {
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+ }
inline unsigned getVPENum(unsigned tid);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index f13653132..b83bb576b 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,8 +32,6 @@
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
@@ -189,9 +187,11 @@ namespace MipsISA
return reg;
}
- void copyRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyMiscRegs(ThreadContext *src, ThreadContext *dest);
} // namespace MipsISA
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 6195c4ceb..300761c93 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -74,8 +74,6 @@ namespace MipsISA {
void startupCPU(ThreadContext *tc, int cpuId);
- void copyRegs(ThreadContext *src, ThreadContext *dest);
-
// Instruction address compression hooks
static inline Addr realPCToFetchPC(const Addr &addr) {
return addr;