Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

1 files changed, 5 insertions, 5 deletions

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5ab6957a3..5d4403553 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -74,10 +74,10 @@ namespace MipsISA
     const int ReturnValueReg = 2;
     const int ReturnValueReg1 = 2;
     const int ReturnValueReg2 = 3;
-    const int ArgumentReg0 = 4;
-    const int ArgumentReg1 = 5;
-    const int ArgumentReg2 = 6;
-    const int ArgumentReg3 = 7;
+
+    const int ArgumentReg[] = {4, 5, 6, 7};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
     const int KernelReg0 = 26;
     const int KernelReg1 = 27;
     const int GlobalPointerReg = 28;
@@ -87,7 +87,7 @@ namespace MipsISA
 
     const int SyscallNumReg = ReturnValueReg1;
     const int SyscallPseudoReturnReg = ReturnValueReg2;
-    const int SyscallSuccessReg = ArgumentReg3;
+    const int SyscallSuccessReg = ArgumentReg[3];
 
     const int LogVMPageSize = 13;	// 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);