diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
| commit | 0b5cf4ba6eb2702ade2bc77c07842edd97eab264 (patch) | |
| tree | 4e1ed8130794049e771759059269e6dc23848180 /src/arch/mips | |
| parent | 76c07ea46bc4f8f6d500f909abfb07addf217940 (diff) | |
| parent | 6c6b78126a38cf92eef89f027312e1c7a063bd18 (diff) | |
| download | gem5-0b5cf4ba6eb2702ade2bc77c07842edd97eab264.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 10 | ||||
| -rw-r--r-- | src/arch/mips/isa/includes.isa | 23 |
2 files changed, 18 insertions, 15 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index d6b0c2938..e786cfbe2 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -162,7 +162,7 @@ def template InitiateAccDeclare {{ def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; }}; @@ -288,7 +288,7 @@ def template LoadInitiateAcc {{ def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -412,7 +412,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -434,7 +434,7 @@ def template StoreCompleteAcc {{ }}; def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -509,7 +509,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, + Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index f58c8adaa..274fdcaa1 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -38,23 +38,25 @@ output header {{ #include <iostream> #include <iomanip> -#include "cpu/static_inst.hh" #include "arch/mips/isa_traits.hh" +#include "cpu/static_inst.hh" +#include "mem/packet.hh" }}; output decoder {{ +#include <cmath> +#if defined(linux) +#include <fenv.h> +#endif + +#include "arch/mips/faults.hh" +#include "arch/mips/isa_traits.hh" +#include "arch/mips/isa_traits.hh" #include "arch/mips/isa_traits.hh" +#include "arch/mips/utility.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" -#include "arch/mips/faults.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/utility.hh" - -#include <math.h> -#if defined(linux) -#include <fenv.h> -#endif using namespace MipsISA; }}; @@ -74,8 +76,9 @@ output exec {{ #endif #include "cpu/base.hh" #include "cpu/exetrace.hh" +#include "mem/packet.hh" +#include "mem/packet_access.hh" #include "sim/sim_exit.hh" -#include "mem/packet_impl.hh" using namespace MipsISA; }}; |