cpu: rename *_DepTag constants to *_Reg_Base

Make these names more meaningful.

Specifically, made these substitutions:

s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;

5 files changed, 23 insertions, 23 deletions

diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index cd6faf0f3..455ed70e7 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -72,11 +72,11 @@ output decoder {{
 
     void MipsStaticInst::printReg(std::ostream &os, int reg) const
     {
-        if (reg < FP_Base_DepTag) {
+        if (reg < FP_Reg_Base) {
             ccprintf(os, "r%d", reg);
         }
         else {
-            ccprintf(os, "f%d", reg - FP_Base_DepTag);
+            ccprintf(os, "f%d", reg - FP_Reg_Base);
         }
     }
 
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 1091e67a0..5ff23ca5e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -385,7 +385,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x8: decode MT_U {
                         0x0: mftc0({{
                             data = xc->readRegOtherThread((RT << 3 | SEL) +
-                                                          Ctrl_Base_DepTag);
+                                                          Misc_Reg_Base);
                         }});
                         0x1: decode SEL {
                             0x0: mftgpr({{
@@ -409,19 +409,19 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: decode MT_H {
                                 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 }});
                                 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
-                                                                             FP_Base_DepTag);
+                                                                             FP_Reg_Base);
                                 }});
                             }
                             0x3: cftc1({{
                                 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 switch (RT) {
                                   case 0:
                                     data = xc->readRegOtherThread(FLOATREG_FIR +
-                                                                  Ctrl_Base_DepTag);
+                                                                  Misc_Reg_Base);
                                     break;
                                   case 25:
                                     data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,7 +450,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format MT_MTTR {
                     // Decode MIPS MT MTTR instruction into sub-instructions
                     0xC: decode MT_U {
-                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
+                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
                                                             Rt);
                                    }});
                         0x1: decode SEL {
@@ -496,10 +496,10 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: mttc1({{
                                 uint64_t data = xc->readRegOtherThread(RD +
-                                                                       FP_Base_DepTag);
+                                                                       FP_Reg_Base);
                                 data = insertBits(data, MT_H ? 63 : 31,
                                                   MT_H ? 32 : 0, Rt);
-                                xc->setRegOtherThread(RD + FP_Base_DepTag,
+                                xc->setRegOtherThread(RD + FP_Reg_Base,
                                                       data);
                             }});
                             0x3: cttc1({{
@@ -534,7 +534,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                             "Access to Floating Control "
                                             "S""tatus Register", FS);
                                 }
-                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
+                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
                             }});
                             default: CP0Unimpl::unknown();
                         }
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index b4d00454e..74163eebf 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -102,7 +102,7 @@ output exec {{
             MVPConf0Reg &mvp_conf0)
     {
         vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
-        tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
+        tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
         tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
         vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
         mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 02e98a170..64c765f19 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -113,23 +113,23 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
     int success = 0;
     for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
         TCBindReg tidTCBind =
-            tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
+            tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
         TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
 
         if (tidTCBind.curVPE == tcBind.curVPE) {
 
             TCStatusReg tidTCStatus =
                 tc->readRegOtherThread(MISCREG_TC_STATUS +
-                                       Ctrl_Base_DepTag,tid);
+                                       Misc_Reg_Base,tid);
 
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid);
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
 
             if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
                 tidTCStatus.a == 0 && success == 0) {
 
                 tc->setRegOtherThread(MISCREG_TC_RESTART +
-                                      Ctrl_Base_DepTag, Rs, tid);
+                                      Misc_Reg_Base, Rs, tid);
                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 
                 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
@@ -149,7 +149,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
                 tidTCStatus.asid = tcStatus.asid;
 
                 // Write Status Register
-                tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                       tidTCStatus, tid);
 
                 // Mark As Successful Fork
@@ -185,13 +185,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 
         for (ThreadID tid = 0; tid < num_threads; tid++) {
             TCStatusReg tidTCStatus =
-                tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                        tid);
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
                                        tid);
             TCBindReg tidTCBind =
-                tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
                                        tid);
 
             if (tidTCBind.curVPE == tcBind.curVPE &&
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 911e09d41..d9d94e47b 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -275,9 +275,9 @@ enum MiscRegIndex{
 const int NumMiscRegs = MISCREG_NUMREGS;
 
 // These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs;
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
+const int FP_Reg_Base = NumIntRegs;
+const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;