arch,cpu: "virtualize" the TLB interface.

CPUs have historically instantiated the architecture specific version
of the TLBs to avoid a virtual function call, making them a little bit
more dependent on what the current ISA is. Some simple performance
measurement, the x86 twolf regression on the atomic CPU, shows that
there isn't actually any performance benefit, and if anything the
simulator goes slightly faster (although still within margin of error)
when the TLB functions are virtual.

This change switches everything outside of the architectures themselves
to use the generic BaseTLB type, and then inside the ISA for them to
cast that to their architecture specific type to call into architecture
specific interfaces.

The ARM TLB needed the most adjustment since it was using non-standard
translation function signatures. Specifically, they all took an extra
"type" parameter which defaulted to normal, and translateTiming
returned a Fault. translateTiming actually doesn't need to return a
Fault because everywhere that consumed it just stored it into a
structure which it then deleted(?), and the fault is stored in the
Translation object when the translation is done.

A little more work is needed to fully obviate the arch/tlb.hh header,
so the TheISA::TLB type is still visible outside of the ISAs.
Specifically, the TlbEntry type is used in the generic PageTable which
lives in src/mem.

Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575
Reviewed-on: https://gem5-review.googlesource.com/6921
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

3 files changed, 18 insertions, 23 deletions

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index a349f1a05..9a059822e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -737,7 +737,8 @@ decode OPCODE_HI default Unknown::unknown() {
                 format CP0TLB {
                     0x01: tlbr({{
                         MipsISA::PTE *PTEntry =
-                            xc->tcBase()->getITBPtr()->
+                            dynamic_cast<MipsISA::TLB *>(
+                                xc->tcBase()->getITBPtr())->
                                 getEntry(Index & 0x7FFFFFFF);
                         if (PTEntry == NULL) {
                             fatal("Invalid PTE Entry received on "
@@ -817,7 +818,8 @@ decode OPCODE_HI default Unknown::unknown() {
                         newEntry.OffsetMask =
                             (1 << newEntry.AddrShiftAmount) - 1;
 
-                        MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
+                        auto ptr = dynamic_cast<MipsISA::TLB *>(
+                            xc->tcBase()->getITBPtr());
                         Config3Reg config3 = Config3;
                         PageGrainReg pageGrain = PageGrain;
                         int SP = 0;
@@ -825,7 +827,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
+                        ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
                     }});
                     0x06: tlbwr({{
                         //Create PTE
@@ -882,7 +884,8 @@ decode OPCODE_HI default Unknown::unknown() {
                         newEntry.OffsetMask =
                             (1 << newEntry.AddrShiftAmount) - 1;
 
-                        MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
+                        auto ptr = dynamic_cast<MipsISA::TLB *>(
+                            xc->tcBase()->getITBPtr());
                         Config3Reg config3 = Config3;
                         PageGrainReg pageGrain = PageGrain;
                         int SP = 0;
@@ -890,7 +893,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        Ptr->insertAt(newEntry, Random, SP);
+                        ptr->insertAt(newEntry, Random, SP);
                     }});
 
                     0x08: tlbp({{
@@ -905,8 +908,9 @@ decode OPCODE_HI default Unknown::unknown() {
                             // Mask off lower 2 bits
                             vpn = ((EntryHi >> 11) & 0xFFFFFFFC);
                         }
-                        tlbIndex = xc->tcBase()->getITBPtr()->
-                                   probeEntry(vpn, entryHi.asid);
+                        tlbIndex = dynamic_cast<MipsISA::TLB *>(
+                            xc->tcBase()->getITBPtr())->
+                            probeEntry(vpn, entryHi.asid);
                         // Check TLB for entry matching EntryHi
                         if (tlbIndex != -1) {
                             Index = tlbIndex;
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 87a459488..a18149dfa 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -329,13 +329,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
-{
-    panic("Not implemented\n");
-    return NoFault;
-}
-
-Fault
 TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 {
     return NoFault;
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index af9183192..626812af8 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -112,15 +112,13 @@ class TLB : public BaseTLB
 
     void regStats() override;
 
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, Mode mode);
-
-    /** Function stub for CheckerCPU compilation issues. MIPS does not
-     *  support the Checker model at the moment.
-     */
-    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
-    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+    Fault translateAtomic(
+            RequestPtr req, ThreadContext *tc, Mode mode) override;
+    void translateTiming(
+            RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode) override;
+    Fault finalizePhysical(
+            RequestPtr req, ThreadContext *tc, Mode mode) const override;
 
   private:
     Fault translateInst(RequestPtr req, ThreadContext *tc);