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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 00:15:50 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 00:15:50 -0700 |
| commit | f338d60930e973d330d13715b8617c22b980dcca (patch) | |
| tree | d0980316aa40ff6f15699b752a2087035a634c65 /src/arch/mips | |
| parent | 020e923ba7f027b7b3b18ccf8ac208c576d75b95 (diff) | |
| download | gem5-f338d60930e973d330d13715b8617c22b980dcca.tar.xz | |
SE/FS: Build the Interrupt objects in SE mode.
Diffstat (limited to 'src/arch/mips')
| -rw-r--r-- | src/arch/mips/SConscript | 6 | ||||
| -rwxr-xr-x | src/arch/mips/interrupts.cc | 1 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 9fc2b71ff..c842c5507 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -34,6 +34,7 @@ Import('*') if env['TARGET_ISA'] == 'mips': Source('faults.cc') + Source('interrupts.cc') Source('isa.cc') Source('tlb.cc') Source('pagetable.cc') @@ -41,19 +42,18 @@ if env['TARGET_ISA'] == 'mips': Source('dsp.cc') Source('remote_gdb.cc') - SimObject('MipsTLB.py') + SimObject('MipsInterrupts.py') DebugFlag('MipsPRA') + SimObject('MipsTLB.py') if env['FULL_SYSTEM']: SimObject('MipsSystem.py') - SimObject('MipsInterrupts.py') Source('idle_event.cc') Source('mips_core_specific.cc') Source('vtophys.cc') Source('system.cc') Source('stacktrace.cc') Source('linux/system.cc') - Source('interrupts.cc') Source('bare_iron/system.cc') else: Source('process.cc') diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index 096aa628f..f4221ab2c 100755 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -36,6 +36,7 @@ #include "arch/mips/pra_constants.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" +#include "debug/Interrupt.hh" namespace MipsISA { |