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authorNathanael Premillieu <nathanael.premillieu@arm.com>2017-04-05 12:46:06 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch)
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/mips
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff)
downloadgem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/mips')
-rw-r--r--src/arch/mips/isa/base.isa10
-rw-r--r--src/arch/mips/isa/decoder.isa181
-rw-r--r--src/arch/mips/isa/formats/int.isa12
-rw-r--r--src/arch/mips/isa/formats/mt.isa3
-rwxr-xr-xsrc/arch/mips/mt.hh23
-rw-r--r--src/arch/mips/registers.hh8
6 files changed, 140 insertions, 97 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 455ed70e7..c0f259666 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -53,7 +53,7 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
- void printReg(std::ostream &os, int reg) const;
+ void printReg(std::ostream &os, RegId reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -70,13 +70,13 @@ output header {{
//Ouputs to decoder.cc
output decoder {{
- void MipsStaticInst::printReg(std::ostream &os, int reg) const
+ void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
{
- if (reg < FP_Reg_Base) {
- ccprintf(os, "r%d", reg);
+ if (reg.regClass == IntRegClass) {
+ ccprintf(os, "r%d", reg.regIdx);
}
else {
- ccprintf(os, "f%d", reg - FP_Reg_Base);
+ ccprintf(os, "f%d", reg.regIdx);
}
}
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 5c3c6f6b1..a349f1a05 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -384,44 +384,86 @@ decode OPCODE_HI default Unknown::unknown() {
// Decode MIPS MT MFTR instruction into sub-instructions
0x8: decode MT_U {
0x0: mftc0({{
- data = xc->readRegOtherThread((RT << 3 | SEL) +
- Misc_Reg_Base);
+ data = xc->readRegOtherThread(RegId(MiscRegClass,
+ (RT << 3 | SEL)));
}});
0x1: decode SEL {
0x0: mftgpr({{
- data = xc->readRegOtherThread(RT);
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, RT));
}});
0x1: decode RT {
- 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
- 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
- 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
- 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
- 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
- 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
- 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
- 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
- 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
- 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
- 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
- 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
- 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
+ 0x0: mftlo_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO0));
+ }});
+ 0x1: mfthi_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI0));
+ }});
+ 0x2: mftacx_dsp0({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX0));
+ }});
+ 0x4: mftlo_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO1));
+ }});
+ 0x5: mfthi_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI1));
+ }});
+ 0x6: mftacx_dsp1({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX1));
+ }});
+ 0x8: mftlo_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO2));
+ }});
+ 0x9: mfthi_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI2));
+ }});
+ 0x10: mftacx_dsp2({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX2));
+ }});
+ 0x12: mftlo_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO3));
+ }});
+ 0x13: mfthi_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI3));
+ }});
+ 0x14: mftacx_dsp3({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX3));
+ }});
+ 0x16: mftdsp({{
+ data = xc->readRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_CONTROL));
+ }});
default: CP0Unimpl::unknown();
}
0x2: decode MT_H {
- 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
- FP_Reg_Base);
+ 0x0: mftc1({{
+ data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RT));
}});
- 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
- FP_Reg_Base);
+ 0x1: mfthc1({{
+ data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RT));
}});
}
0x3: cftc1({{
- uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
- FP_Reg_Base);
+ uint32_t fcsr_val = xc->readRegOtherThread(
+ RegId(FloatRegClass, FLOATREG_FCSR));
switch (RT) {
case 0:
- data = xc->readRegOtherThread(FLOATREG_FIR +
- Misc_Reg_Base);
+ data = xc->readRegOtherThread(
+ RegId(MiscRegClass, FLOATREG_FIR));
break;
case 25:
data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,56 +492,62 @@ decode OPCODE_HI default Unknown::unknown() {
format MT_MTTR {
// Decode MIPS MT MTTR instruction into sub-instructions
0xC: decode MT_U {
- 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
- Rt);
+ 0x0: mttc0({{ xc->setRegOtherThread(
+ RegId(MiscRegClass, (RD << 3 | SEL)), Rt);
}});
0x1: decode SEL {
- 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
+ 0x0: mttgpr({{ xc->setRegOtherThread(
+ RegId(IntRegClass, RD), Rt);
+ }});
0x1: decode RT {
- 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
- }});
- 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
- Rt);
- }});
- 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
- Rt);
- }});
- 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
- Rt);
- }});
- 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
- Rt);
- }});
- 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
- Rt);
- }});
- 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
- Rt);
- }});
- 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
- Rt);
- }});
- 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
- Rt);
- }});
- 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
- Rt);
- }});
- 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
- Rt);
- }});
- 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
- }});
- 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
+ 0x0: mttlo_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO0), Rt);
+ }});
+ 0x1: mtthi_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI0), Rt);
+ }});
+ 0x2: mttacx_dsp0({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX0), Rt);
+ }});
+ 0x4: mttlo_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO1), Rt);
+ }});
+ 0x5: mtthi_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI1), Rt);
+ }});
+ 0x6: mttacx_dsp1({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX1), Rt);
+ }});
+ 0x8: mttlo_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO2), Rt);
+ }});
+ 0x9: mtthi_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI2), Rt);
+ }});
+ 0x10: mttacx_dsp2({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX2), Rt);
+ }});
+ 0x12: mttlo_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_LO3), Rt);
+ }});
+ 0x13: mtthi_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_HI3), Rt);
+ }});
+ 0x14: mttacx_dsp3({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_ACX3), Rt);
+ }});
+ 0x16: mttdsp({{ xc->setRegOtherThread(
+ RegId(IntRegClass, INTREG_DSP_CONTROL), Rt);
+ }});
default: CP0Unimpl::unknown();
}
0x2: mttc1({{
- uint64_t data = xc->readRegOtherThread(RD +
- FP_Reg_Base);
+ uint64_t data = xc->readRegOtherThread(
+ RegId(FloatRegClass, RD));
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
- xc->setRegOtherThread(RD + FP_Reg_Base,
+ xc->setRegOtherThread(RegId(FloatRegClass, RD),
data);
}});
0x3: cttc1({{
@@ -534,7 +582,8 @@ decode OPCODE_HI default Unknown::unknown() {
"Access to Floating Control "
"S""tatus Register", FS);
}
- xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
+ xc->setRegOtherThread(
+ RegId(FloatRegClass, FLOATREG_FCSR), data);
}});
default: CP0Unimpl::unknown();
}
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 52358bbdb..641608e89 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -257,9 +257,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -272,9 +272,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
@@ -287,9 +287,9 @@ output decoder {{
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
printReg(ss, _srcRegIdx[0]);
}
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 8d2254cb4..b34773ef5 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -102,7 +102,8 @@ output exec {{
MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
- tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
+ tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass,
+ MISCREG_TC_BIND));
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index cc72d7a5d..7b28b0493 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -113,24 +113,25 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
int success = 0;
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
TCBindReg tidTCBind =
- tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND), tid);
TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
if (tidTCBind.curVPE == tcBind.curVPE) {
TCStatusReg tidTCStatus =
- tc->readRegOtherThread(MISCREG_TC_STATUS +
- Misc_Reg_Base,tid);
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
+ tid);
TCHaltReg tidTCHalt =
- tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT),
+ tid);
if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
tidTCStatus.a == 0 && success == 0) {
- tc->setRegOtherThread(MISCREG_TC_RESTART +
- Misc_Reg_Base, Rs, tid);
- tc->setRegOtherThread(Rd_bits, Rt, tid);
+ tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_RESTART),
+ Rs, tid);
+ tc->setRegOtherThread(RegId(IntRegClass, Rd_bits), Rt, tid);
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
@@ -149,7 +150,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
tidTCStatus.asid = tcStatus.asid;
// Write Status Register
- tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
+ tc->setRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
tidTCStatus, tid);
// Mark As Successful Fork
@@ -185,13 +186,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
for (ThreadID tid = 0; tid < num_threads; tid++) {
TCStatusReg tidTCStatus =
- tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_STATUS),
tid);
TCHaltReg tidTCHalt =
- tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_HALT),
tid);
TCBindReg tidTCBind =
- tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
+ tc->readRegOtherThread(RegId(MiscRegClass, MISCREG_TC_BIND),
tid);
if (tidTCBind.curVPE == tcBind.curVPE &&
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 0ac84cc7f..c7cdb6522 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -275,16 +275,8 @@ enum MiscRegIndex{
const int NumMiscRegs = MISCREG_NUMREGS;
-// These help enumerate all the registers for dependence tracking.
-const int FP_Reg_Base = NumIntRegs;
-const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
-const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
-
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-typedef uint16_t RegIndex;
-
typedef uint32_t IntReg;
// floating point register file entry type
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 19:12:25 +0000