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authorMitch Hayenga <mitch.hayenga@arm.com>2016-07-21 17:19:15 +0100
committerMitch Hayenga <mitch.hayenga@arm.com>2016-07-21 17:19:15 +0100
commit8a476d387c84f037d0ccf3cc20dc88870ab45fec (patch)
tree341d4975740d91056a44b13bd43e10bf175d7166 /src/arch/mips
parentd25b58036a040d8ac733b824e2865e1f5fe43e00 (diff)
downloadgem5-8a476d387c84f037d0ccf3cc20dc88870ab45fec.tar.xz
isa: Modify get/check interrupt routines
Make it so that getInterrupt *always* returns an interrupt if checkInterrupts() returns true. This fixes/simplifies handling of interrupts on the SMT FS CPUs (currently minor).
Diffstat (limited to 'src/arch/mips')
-rwxr-xr-xsrc/arch/mips/interrupts.cc31
-rwxr-xr-xsrc/arch/mips/interrupts.hh8
2 files changed, 22 insertions, 17 deletions
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index a0d9de03b..98c1b8e23 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -105,11 +105,11 @@ Interrupts::clearAll()
}
-
-Fault
-Interrupts::getInterrupt(ThreadContext * tc)
+bool
+Interrupts::checkInterrupts(ThreadContext *tc) const
{
- DPRINTF(Interrupt, "Interrupts getInterrupt\n");
+ if (!interruptsPending(tc))
+ return false;
//Check if there are any outstanding interrupts
StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
@@ -120,14 +120,25 @@ Interrupts::getInterrupt(ThreadContext * tc)
// So if any interrupt that isn't masked is detected, jump to interrupt
// handler
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
- if (status.im && cause.ip) {
- DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
- (unsigned)status.im, (unsigned)cause.ip);
- return std::make_shared<InterruptFault>();
- }
+ if (status.im && cause.ip)
+ return true;
+
}
- return NoFault;
+ return false;
+}
+
+Fault
+Interrupts::getInterrupt(ThreadContext * tc)
+{
+ assert(checkInterrupts(tc));
+
+ StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
+ CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
+ DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
+ (unsigned)status.im, (unsigned)cause.ip);
+
+ return std::make_shared<InterruptFault>();
}
bool
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index b5323e4e1..2205510d2 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -107,13 +107,7 @@ class Interrupts : public SimObject
void updateIntrInfo(ThreadContext *tc) const;
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
-
- bool
- checkInterrupts(ThreadContext *tc) const
- {
- return interruptsPending(tc);
- }
-
+ bool checkInterrupts(ThreadContext *tc) const;
void
serialize(CheckpointOut &cp) const override