cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

3 files changed, 12 insertions, 9 deletions

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index feb55e473..c751cb168 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -37,6 +37,7 @@
 
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
+#include "cpu/reg_class.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 
@@ -165,6 +166,8 @@ namespace MipsISA
 
         ISA(Params *p);
 
+        RegId flattenRegId(const RegId& regId) const { return regId; }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index c0f259666..946dce6df 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -72,11 +72,11 @@ output decoder {{
 
     void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
     {
-        if (reg.regClass == IntRegClass) {
-            ccprintf(os, "r%d", reg.regIdx);
+        if (reg.isIntReg()) {
+            ccprintf(os, "r%d", reg.index());
         }
         else {
-            ccprintf(os, "f%d", reg.regIdx);
+            ccprintf(os, "f%d", reg.index());
         }
     }
 
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 641608e89..c21c1255b 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -257,9 +257,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }
 
@@ -272,9 +272,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }
 
@@ -287,9 +287,9 @@ output decoder {{
 
             ccprintf(ss, "%-10s ", mnemonic);
 
-            if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) {
+            if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
                 printReg(ss, _destRegIdx[0]);
-            } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) {
+            } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
                 printReg(ss, _srcRegIdx[0]);
             }