POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.

14 files changed, 1528 insertions, 0 deletions

diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
new file mode 100644
index 000000000..3f4346c97
--- /dev/null
+++ b/src/arch/power/insts/branch.cc
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/branch.hh"
+#include "base/loader/symtab.hh"
+
+using namespace PowerISA;
+
+const std::string &
+PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+    if (!cachedDisassembly ||
+        pc != cachedPC || symtab != cachedSymtab)
+    {
+        if (cachedDisassembly)
+            delete cachedDisassembly;
+
+        cachedDisassembly =
+            new std::string(generateDisassembly(pc, symtab));
+        cachedPC = pc;
+        cachedSymtab = symtab;
+    }
+
+    return *cachedDisassembly;
+}
+
+Addr
+BranchPCRel::branchTarget(Addr pc) const
+{
+    return (uint32_t)(pc + disp);
+}
+
+std::string
+BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    Addr target = pc + disp;
+
+    std::string str;
+    if (symtab && symtab->findSymbol(target, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", target);
+
+    return ss.str();
+}
+
+Addr
+BranchNonPCRel::branchTarget(Addr pc) const
+{
+    return targetAddr;
+}
+
+std::string
+BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    std::string str;
+    if (symtab && symtab->findSymbol(targetAddr, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", targetAddr);
+
+    return ss.str();
+}
+
+Addr
+BranchPCRelCond::branchTarget(Addr pc) const
+{
+    return (uint32_t)(pc + disp);
+}
+
+std::string
+BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    Addr target = pc + disp;
+
+    std::string str;
+    if (symtab && symtab->findSymbol(target, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", target);
+
+    return ss.str();
+}
+
+Addr
+BranchNonPCRelCond::branchTarget(Addr pc) const
+{
+    return targetAddr;
+}
+
+std::string
+BranchNonPCRelCond::generateDisassembly(Addr pc,
+                                        const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    std::string str;
+    if (symtab && symtab->findSymbol(targetAddr, str))
+        ss << str;
+    else
+        ccprintf(ss, "0x%x", targetAddr);
+
+    return ss.str();
+}
+
+Addr
+BranchRegCond::branchTarget(ThreadContext *tc) const
+{
+    uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]);
+    return (regVal & 0xfffffffc);
+}
+
+std::string
+BranchRegCond::generateDisassembly(Addr pc,
+                                   const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    ss << bo << ", " << bi << ", ";
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
new file mode 100644
index 000000000..dd00e42c3
--- /dev/null
+++ b/src/arch/power/insts/branch.hh
@@ -0,0 +1,241 @@
+/* Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_INSTS_BRANCH_HH__
+#define __ARCH_POWER_INSTS_BRANCH_HH__
+
+#include "arch/power/insts/static_inst.hh"
+
+namespace PowerISA
+{
+
+/**
+ * Base class for instructions whose disassembly is not purely a
+ * function of the machine instruction (i.e., it depends on the
+ * PC).  This class overrides the disassemble() method to check
+ * the PC and symbol table values before re-using a cached
+ * disassembly string.  This is necessary for branches and jumps,
+ * where the disassembly string includes the target address (which
+ * may depend on the PC and/or symbol table).
+ */
+class PCDependentDisassembly : public PowerStaticInst
+{
+  protected:
+    /// Cached program counter from last disassembly
+    mutable Addr cachedPC;
+    /// Cached symbol table pointer from last disassembly
+    mutable const SymbolTable *cachedSymtab;
+
+    /// Constructor
+    PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
+                           OpClass __opClass)
+        : PowerStaticInst(mnem, _machInst, __opClass),
+          cachedPC(0), cachedSymtab(0)
+    {
+    }
+
+    const std::string &
+    disassemble(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for unconditional, PC-relative branches.
+ */
+class BranchPCRel : public PCDependentDisassembly
+{
+  protected:
+
+    /// Displacement
+    uint32_t disp;
+
+    /// Constructor.
+    BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : PCDependentDisassembly(mnem, _machInst, __opClass),
+          disp(machInst.li << 2)
+    {
+        // If bit 26 is 1 then sign extend
+        if (disp & 0x2000000) {
+            disp |= 0xfc000000;
+        }
+    }
+
+    Addr branchTarget(Addr pc) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for unconditional, non PC-relative branches.
+ */
+class BranchNonPCRel : public PCDependentDisassembly
+{
+  protected:
+
+    /// Target address
+    uint32_t targetAddr;
+
+    /// Constructor.
+    BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : PCDependentDisassembly(mnem, _machInst, __opClass),
+          targetAddr(machInst.li << 2)
+    {
+        // If bit 26 is 1 then sign extend
+        if (targetAddr & 0x2000000) {
+            targetAddr |= 0xfc000000;
+        }
+    }
+
+    Addr branchTarget(Addr pc) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for conditional branches.
+ */
+class BranchCond : public PCDependentDisassembly
+{
+  protected:
+
+    /// Fields needed for conditions
+    uint32_t bo;
+    uint32_t bi;
+
+    /// Constructor.
+    BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : PCDependentDisassembly(mnem, _machInst, __opClass),
+          bo(machInst.bo),
+          bi(machInst.bi)
+    {
+    }
+
+    inline bool
+    ctrOk(uint32_t& ctr) const
+    {
+        bool ctr_ok;
+        if (bo & 4) {
+            ctr_ok = true;
+        } else {
+            ctr--;
+            if (ctr != 0) {
+                ctr_ok = ((bo & 2) == 0);
+            } else {
+                ctr_ok = ((bo & 2) != 0);
+            }
+        }
+        return ctr_ok;
+    }
+
+    inline bool
+    condOk(uint32_t cr) const
+    {
+        bool cond_ok;
+        if (bo & 16) {
+            cond_ok = true;
+        } else {
+            cond_ok = (((cr >> (31 - bi)) & 1) == ((bo >> 3) & 1));
+        }
+        return cond_ok;
+    }
+};
+
+/**
+ * Base class for conditional, PC-relative branches.
+ */
+class BranchPCRelCond : public BranchCond
+{
+  protected:
+
+    /// Displacement
+    uint32_t disp;
+
+    /// Constructor.
+    BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : BranchCond(mnem, _machInst, __opClass),
+          disp(machInst.bd << 2)
+    {
+        // If bit 16 is 1 then sign extend
+        if (disp & 0x8000) {
+            disp |= 0xffff0000;
+        }
+    }
+
+    Addr branchTarget(Addr pc) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for conditional, non PC-relative branches.
+ */
+class BranchNonPCRelCond : public BranchCond
+{
+  protected:
+
+    /// Target address
+    uint32_t targetAddr;
+
+    /// Constructor.
+    BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : BranchCond(mnem, _machInst, __opClass),
+          targetAddr(machInst.bd << 2)
+    {
+        // If bit 16 is 1 then sign extend
+        if (targetAddr & 0x8000) {
+            targetAddr |= 0xffff0000;
+        }
+    }
+
+    Addr branchTarget(Addr pc) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for conditional, register-based branches
+ */
+class BranchRegCond : public BranchCond
+{
+  protected:
+
+    /// Constructor.
+    BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : BranchCond(mnem, _machInst, __opClass)
+    {
+    }
+
+    Addr branchTarget(ThreadContext *tc) const;
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_BRANCH_HH__
diff --git a/src/arch/power/insts/condition.cc b/src/arch/power/insts/condition.cc
new file mode 100644
index 000000000..0a942a982
--- /dev/null
+++ b/src/arch/power/insts/condition.cc
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/condition.hh"
+
+using namespace PowerISA;
+
+std::string
+CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Format is <mnemonic> bt, ba, bb
+    ss << bt << ", " << ba << ", " << bb;
+
+    return ss.str();
+}
+
+std::string
+CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Format is <mnemonic> bf, bfa
+    ss << bf << ", " << bfa;
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
new file mode 100644
index 000000000..a23667d9e
--- /dev/null
+++ b/src/arch/power/insts/condition.hh
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_INSTS_CONDITION_HH__
+#define __ARCH_POWER_INSTS_CONDITION_HH__
+
+#include "arch/power/insts/static_inst.hh"
+#include "base/cprintf.hh"
+
+namespace PowerISA
+{
+
+/**
+ * Class for condition register logical operations.
+ */
+class CondLogicOp : public PowerStaticInst
+{
+  protected:
+
+    uint32_t ba;
+    uint32_t bb;
+    uint32_t bt;
+
+    /// Constructor
+    CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : PowerStaticInst(mnem, _machInst, __opClass),
+        ba(machInst.ba),
+        bb(machInst.bb),
+        bt(machInst.bt)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Class for condition register move operations.
+ */
+class CondMoveOp : public PowerStaticInst
+{
+  protected:
+
+    uint32_t bf;
+    uint32_t bfa;
+
+    /// Constructor
+    CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : PowerStaticInst(mnem, _machInst, __opClass),
+        bf(machInst.bf),
+        bfa(machInst.bfa)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_CONDITION_HH__
diff --git a/src/arch/power/insts/floating.cc b/src/arch/power/insts/floating.cc
new file mode 100644
index 000000000..f5c34ee2a
--- /dev/null
+++ b/src/arch/power/insts/floating.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/floating.hh"
+
+using namespace PowerISA;
+
+std::string
+FloatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the (possibly) two source registers
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+        if (_numSrcRegs > 1) {
+          ss << ", ";
+          printReg(ss, _srcRegIdx[1]);
+        }
+    }
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
new file mode 100644
index 000000000..2b2668409
--- /dev/null
+++ b/src/arch/power/insts/floating.hh
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ *          Korey Sewell
+ */
+
+#ifndef __ARCH_POWER_INSTS_FLOATING_HH__
+#define __ARCH_POWER_INSTS_FLOATING_HH__
+
+#include "arch/power/insts/static_inst.hh"
+#include "base/cprintf.hh"
+#include "base/bitfield.hh"
+
+namespace PowerISA
+{
+
+/**
+ * Base class for floating point operations.
+ */
+class FloatOp : public PowerStaticInst
+{
+  protected:
+
+    bool rcSet;
+
+    /// Constructor
+    FloatOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : PowerStaticInst(mnem, _machInst, __opClass)
+    {
+    }
+
+    // Test for NaN (maximum biased exponent & non-zero fraction)
+    inline bool
+    isNan(uint32_t val_bits) const
+    {
+        return ((bits(val_bits, 30, 23) == 0xFF) && bits(val_bits, 22, 0));
+    }
+
+    inline bool
+    isNan(uint64_t val_bits) const
+    {
+        return ((bits(val_bits, 62, 52) == 0x7FF) && bits(val_bits, 51, 0));
+    }
+
+    inline bool
+    isNan(float val) const
+    {
+        void *val_ptr = &val;
+        uint32_t val_bits = *(uint32_t *) val_ptr;
+        return isNan(val_bits);
+    }
+
+    inline bool
+    isNan(double val) const
+    {
+        void *val_ptr = &val;
+        uint64_t val_bits = *(uint64_t *) val_ptr;
+        return isNan(val_bits);
+    }
+
+    // Test for SNaN (NaN with high order bit of fraction set to 0)
+    inline bool
+    isSnan(uint32_t val_bits) const
+    {
+        return ((bits(val_bits, 30, 22) == 0x1FE) && bits(val_bits, 22, 0));
+    }
+
+    // Test for QNaN (NaN with high order bit of fraction set to 1)
+    inline bool
+    isQnan(uint32_t val_bits) const
+    {
+        return (bits(val_bits, 30, 22) == 0x1FF);
+    }
+
+    // Test for infinity (maximum biased exponent and zero fraction)
+    inline bool
+    isInfinity(uint32_t val_bits) const
+    {
+        return ((bits(val_bits, 30, 23) == 0xFF) && !bits(val_bits, 22, 0));
+    }
+
+    // Test for normalized numbers (biased exponent in the range 1 to 254)
+    inline bool
+    isNormalized(uint32_t val_bits) const
+    {
+        return ((bits(val_bits, 30, 23) != 0xFF) && bits(val_bits, 22, 0));
+    }
+
+    // Test for denormalized numbers (biased exponent of zero and
+    // non-zero fraction)
+    inline bool
+    isDenormalized(uint32_t val_bits) const
+    {
+        return (!bits(val_bits, 30, 23) && bits(val_bits, 22, 0));
+    }
+
+    // Test for zero (biased exponent of zero and fraction of zero)
+    inline bool
+    isZero(uint32_t val_bits) const
+    {
+        return (!bits(val_bits, 30, 23) && !bits(val_bits, 22, 0));
+    }
+
+    // Test for negative
+    inline bool
+    isNegative(uint32_t val_bits) const
+    {
+        return (bits(val_bits, 31));
+    }
+
+    // Compute the CR field
+    inline uint32_t
+    makeCRField(double a, double b) const
+    {
+        uint32_t c = 0;
+        if (isNan(a) || isNan(b)) { c = 0x1; }
+        else if (a < b)           { c = 0x8; }
+        else if (a > b)           { c = 0x4; }
+        else                      { c = 0x2; }
+        return c;
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_FLOATING_HH__
diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
new file mode 100644
index 000000000..1f81a15dc
--- /dev/null
+++ b/src/arch/power/insts/integer.cc
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/integer.hh"
+
+using namespace std;
+using namespace PowerISA;
+
+string
+IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    bool printDest = true;
+    bool printSrcs = true;
+    bool printSecondSrc = true;
+
+    // Generate the correct mnemonic
+    string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
+        myMnemonic = "mr";
+        printSecondSrc = false;
+    } else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi")) {
+        printDest = false;
+    } else if (!myMnemonic.compare("mflr")) {
+        printSrcs = false;
+    }
+
+    // Additional characters depending on isa bits being set
+    if (oeSet) myMnemonic = myMnemonic + "o";
+    if (rcSet) myMnemonic = myMnemonic + ".";
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0 && printDest) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the (possibly) two source registers
+    if (_numSrcRegs > 0 && printSrcs) {
+        if (_numDestRegs > 0 && printDest) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+        if (_numSrcRegs > 1 && printSecondSrc) {
+          ss << ", ";
+          printReg(ss, _srcRegIdx[1]);
+        }
+    }
+
+    return ss.str();
+}
+
+
+string
+IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+
+    // Generate the correct mnemonic
+    string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
+        myMnemonic = "li";
+    } else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
+        myMnemonic = "lis";
+    }
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the source register
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+    }
+
+    // Print the immediate value last
+    ss << ", " << (int32_t)imm;
+
+    return ss.str();
+}
+
+
+string
+IntShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the first source register
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+    }
+
+    // Print the shift
+    ss << ", " << sh;
+
+    return ss.str();
+}
+
+
+string
+IntRotateOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the first source register
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+    }
+
+    // Print the shift, mask begin and mask end
+    ss << ", " << sh << ", " << mb << ", " << me;
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
new file mode 100644
index 000000000..b4b96d5dc
--- /dev/null
+++ b/src/arch/power/insts/integer.hh
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_INSTS_INTEGER_HH__
+#define __ARCH_POWER_INSTS_INTEGER_HH__
+
+#include "arch/power/insts/static_inst.hh"
+#include "base/cprintf.hh"
+#include "base/bitfield.hh"
+
+namespace PowerISA
+{
+
+/**
+ * We provide a base class for integer operations and then inherit for
+ * several other classes. These specialise for instructions using immediate
+ * values and also rotate instructions. We also need to have versions that
+ * consider the Rc and OE bits.
+ */
+
+/**
+ * Base class for integer operations.
+ */
+class IntOp : public PowerStaticInst
+{
+  protected:
+
+    bool rcSet;
+    bool oeSet;
+
+    // Needed for srawi only
+    uint32_t sh;
+
+    /// Constructor
+    IntOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : PowerStaticInst(mnem, _machInst, __opClass),
+        rcSet(false), oeSet(false)
+    {
+    }
+
+    /* Compute the CR (condition register) field using signed comparison */
+    inline uint32_t
+    makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+    {
+        uint32_t c = xerSO;
+
+        /* We've pre-shifted the immediate values here */
+        if (a < b)      { c += 0x8; }
+        else if (a > b) { c += 0x4; }
+        else            { c += 0x2; }
+        return c;
+    }
+
+    /* Compute the CR (condition register) field using unsigned comparison */
+    inline uint32_t
+    makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+    {
+        uint32_t c = xerSO;
+
+        /* We've pre-shifted the immediate values here */
+        if (a < b)      { c += 0x8; }
+        else if (a > b) { c += 0x4; }
+        else            { c += 0x2; }
+        return c;
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+
+/**
+ * Class for integer immediate (signed and unsigned) operations.
+ */
+class IntImmOp : public IntOp
+{
+  protected:
+
+    int32_t imm;
+    uint32_t uimm;
+
+    /// Constructor
+    IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntOp(mnem, _machInst, __opClass),
+        imm(sext<16>(machInst.si)),
+        uimm(machInst.si)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+
+/**
+ * Class for integer operations with a shift.
+ */
+class IntShiftOp : public IntOp
+{
+  protected:
+
+    uint32_t sh;
+
+    /// Constructor
+    IntShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntOp(mnem, _machInst, __opClass),
+        sh(machInst.sh)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+
+/**
+ * Class for integer rotate operations.
+ */
+class IntRotateOp : public IntShiftOp
+{
+  protected:
+
+    uint32_t mb;
+    uint32_t me;
+    uint32_t fullMask;
+
+    /// Constructor
+    IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntShiftOp(mnem, _machInst, __opClass),
+        mb(machInst.mb),
+        me(machInst.me)
+    {
+        if (me >= mb) {
+            fullMask = mask(31 - mb, 31 - me);
+        } else {
+            fullMask = ~mask(31 - (me + 1), 31 - (mb - 1));
+        }
+    }
+
+    uint32_t
+    rotateValue(uint32_t rs, uint32_t shift) const
+    {
+        uint32_t n = shift & 31;
+        return (rs << n) | (rs >> (32 - n));
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_INTEGER_HH__
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
new file mode 100644
index 000000000..447efa2f4
--- /dev/null
+++ b/src/arch/power/insts/mem.cc
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/mem.hh"
+#include "base/loader/symtab.hh"
+
+using namespace PowerISA;
+
+std::string
+MemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    return csprintf("%-10s", mnemonic);
+}
+
+std::string
+MemDispOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Print the destination only for a load
+    if (!flags[IsStore]) {
+        if (_numDestRegs > 0) {
+
+            // If the instruction updates the source register with the
+            // EA, then this source register is placed in position 0,
+            // therefore we print the last destination register.
+            printReg(ss, _destRegIdx[_numDestRegs-1]);
+        }
+    }
+
+    // Print the data register for a store
+    else {
+        printReg(ss, _srcRegIdx[1]);
+    }
+
+    // Print the displacement
+    ss << ", " << (int32_t)disp;
+
+    // Print the address register
+    ss << "(";
+    printReg(ss, _srcRegIdx[0]);
+    ss << ")";
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
new file mode 100644
index 000000000..329dafe57
--- /dev/null
+++ b/src/arch/power/insts/mem.hh
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_MEM_HH__
+#define __ARCH_POWER_MEM_HH__
+
+#include "arch/power/insts/static_inst.hh"
+
+namespace PowerISA
+{
+
+/**
+ * Base class for memory operations.
+ */
+class MemOp : public PowerStaticInst
+{
+  protected:
+
+    /// Memory request flags.  See mem_req_base.hh.
+    unsigned memAccessFlags;
+    /// Pointer to EAComp object.
+    const StaticInstPtr eaCompPtr;
+    /// Pointer to MemAcc object.
+    const StaticInstPtr memAccPtr;
+
+    /// Constructor
+    MemOp(const char *mnem, MachInst _machInst, OpClass __opClass,
+          StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+          StaticInstPtr _memAccPtr = nullStaticInstPtr)
+      : PowerStaticInst(mnem, _machInst, __opClass),
+        memAccessFlags(0),
+        eaCompPtr(_eaCompPtr),
+        memAccPtr(_memAccPtr)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+
+/**
+ * Class for memory operations with displacement.
+ */
+class MemDispOp : public MemOp
+{
+  protected:
+
+    int16_t disp;
+
+    /// Constructor
+    MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass,
+              StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+              StaticInstPtr _memAccPtr = nullStaticInstPtr)
+      : MemOp(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
+        disp(machInst.d)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/insts/misc.cc b/src/arch/power/insts/misc.cc
new file mode 100644
index 000000000..913030b61
--- /dev/null
+++ b/src/arch/power/insts/misc.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/misc.hh"
+
+using namespace PowerISA;
+
+std::string
+MiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the (possibly) two source registers
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+        if (_numSrcRegs > 1) {
+          ss << ", ";
+          printReg(ss, _srcRegIdx[1]);
+        }
+    }
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
new file mode 100644
index 000000000..dd4941b93
--- /dev/null
+++ b/src/arch/power/insts/misc.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_INSTS_MISC_HH__
+#define __ARCH_POWER_INSTS_MISC_HH__
+
+#include "arch/power/insts/static_inst.hh"
+
+namespace PowerISA
+{
+
+/**
+ * Class for misc operations.
+ */
+class MiscOp : public PowerStaticInst
+{
+  protected:
+
+    /// Constructor
+    MiscOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : PowerStaticInst(mnem, _machInst, __opClass)
+    {
+    }
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_MISC_HH__
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
new file mode 100644
index 000000000..1982744bf
--- /dev/null
+++ b/src/arch/power/insts/static_inst.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#include "arch/power/insts/static_inst.hh"
+
+using namespace PowerISA;
+
+void
+PowerStaticInst::printReg(std::ostream &os, int reg) const
+{
+    if (reg < FP_Base_DepTag) {
+        ccprintf(os, "r%d", reg);
+    } else if (reg < Ctrl_Base_DepTag) {
+        ccprintf(os, "f%d", reg - FP_Base_DepTag);
+    } else {
+        switch (reg - Ctrl_Base_DepTag) {
+        case 0: ccprintf(os, "cr"); break;
+        case 1: ccprintf(os, "xer"); break;
+        case 2: ccprintf(os, "lr"); break;
+        case 3: ccprintf(os, "ctr"); break;
+        default: ccprintf(os, "unknown_reg");
+        }
+    }
+}
+
+std::string
+PowerStaticInst::generateDisassembly(Addr pc,
+                                       const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+
+    ccprintf(ss, "%-10s ", mnemonic);
+
+    return ss.str();
+}
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
new file mode 100644
index 000000000..399e75371
--- /dev/null
+++ b/src/arch/power/insts/static_inst.hh
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_INSTS_STATICINST_HH__
+#define __ARCH_POWER_INSTS_STATICINST_HH__
+
+#include "base/trace.hh"
+#include "cpu/static_inst.hh"
+
+namespace PowerISA
+{
+
+class PowerStaticInst : public StaticInst
+{
+  protected:
+
+    // Constructor
+    PowerStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : StaticInst(mnem, _machInst, __opClass)
+    {
+    }
+
+    // Insert a condition value into a CR (condition register) field
+    inline uint32_t
+    insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
+    {
+        uint32_t bits = value << ((7 - bf) * 4);
+        uint32_t mask = ~(0xf << ((7 - bf) * 4));
+        return (cr & mask) | bits;
+    }
+
+    /// Print a register name for disassembly given the unique
+    /// dependence tag number (FP or int).
+    void
+    printReg(std::ostream &os, int reg) const;
+
+    std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+} // PowerISA namespace
+
+#endif //__ARCH_POWER_INSTS_STATICINST_HH__