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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/power/insts | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/power/insts')
| -rw-r--r-- | src/arch/power/insts/branch.cc | 2 | ||||
| -rw-r--r-- | src/arch/power/insts/static_inst.cc | 12 | ||||
| -rw-r--r-- | src/arch/power/insts/static_inst.hh | 2 |
3 files changed, 7 insertions, 9 deletions
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index f9876db8c..f10e8453a 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc, PowerISA::PCState BranchRegCond::branchTarget(ThreadContext *tc) const { - uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); + uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx); return regVal & 0xfffffffc; } diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc index db8c03002..210205db2 100644 --- a/src/arch/power/insts/static_inst.cc +++ b/src/arch/power/insts/static_inst.cc @@ -36,19 +36,17 @@ using namespace PowerISA; void -PowerStaticInst::printReg(std::ostream &os, int reg) const +PowerStaticInst::printReg(std::ostream &os, RegId reg) const { - RegIndex rel_reg; - - switch (regIdxToClass(reg, &rel_reg)) { + switch (reg.regClass) { case IntRegClass: - ccprintf(os, "r%d", rel_reg); + ccprintf(os, "r%d", reg.regIdx); break; case FloatRegClass: - ccprintf(os, "f%d", rel_reg); + ccprintf(os, "f%d", reg.regIdx); break; case MiscRegClass: - switch (rel_reg) { + switch (reg.regIdx) { case 0: ccprintf(os, "cr"); break; case 1: ccprintf(os, "xer"); break; case 2: ccprintf(os, "lr"); break; diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh index 48e5fa94b..b7a818a2c 100644 --- a/src/arch/power/insts/static_inst.hh +++ b/src/arch/power/insts/static_inst.hh @@ -59,7 +59,7 @@ class PowerStaticInst : public StaticInst /// Print a register name for disassembly given the unique /// dependence tag number (FP or int). void - printReg(std::ostream &os, int reg) const; + printReg(std::ostream &os, RegId reg) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; |