diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-26 05:35:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-26 05:35:24 -0400 |
| commit | 312efd742eedef23768a62453404dd2f77ae8b35 (patch) | |
| tree | 22f6e4f65ec6070615b69cb040150c7175acc989 /src/arch/power/isa/decoder.isa | |
| parent | ca9790a2db94e9fad36aa121e934f105348bdead (diff) | |
| download | gem5-312efd742eedef23768a62453404dd2f77ae8b35.tar.xz | |
Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
Diffstat (limited to 'src/arch/power/isa/decoder.isa')
| -rw-r--r-- | src/arch/power/isa/decoder.isa | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 23089190f..11d222390 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -571,14 +571,15 @@ decode OPCODE default Unknown::unknown() { }}); 583: mffs({{ Ft_uq = FPSCR; }}); 134: mtfsfi({{ - FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD); + FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)), + U_FIELD); }}); 711: mtfsf({{ - if (L == 1) { FPSCR = Fb_uq; } + if (L_FIELD == 1) { FPSCR = Fb_uq; } else { for (int i = 0; i < 8; ++i) { if (bits(FLM, i) == 1) { - int k = 4 * (i + (8 * (1 - W))); + int k = 4 * (i + (8 * (1 - W_FIELD))); FPSCR = insertBits(FPSCR, k, k + 3, bits(Fb_uq, k, k + 3)); } |