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author | Gabe Black <gblack@eecs.umich.edu> | 2011-07-02 22:34:29 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-07-02 22:34:29 -0700 |
commit | aade13769fc6c666bb855e0745e042c82f9941d6 (patch) | |
tree | b95bd2ff43f1bb84b5d2615e12a6f7788a33a12e /src/arch/power/isa/formats | |
parent | d42e471baac69f3f853592ae001e8c5c61377cae (diff) | |
download | gem5-aade13769fc6c666bb855e0745e042c82f9941d6.tar.xz |
ISA: Use readBytes/writeBytes for all instruction level memory operations.
Diffstat (limited to 'src/arch/power/isa/formats')
-rw-r--r-- | src/arch/power/isa/formats/mem.isa | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index 014e4ff5a..519275a16 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -84,7 +84,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -109,7 +109,7 @@ def template LoadInitiateAcc {{ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); xc->setEA(EA); } @@ -132,7 +132,7 @@ def template LoadCompleteAcc {{ EA = xc->getEA(); - val = pkt->get<uint%(mem_acc_size)d_t>(); + getMem(pkt, val, traceData); *((uint%(mem_acc_size)d_t*)&Mem) = val; if (fault == NoFault) { @@ -164,8 +164,8 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, NULL); + fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + NULL); } if (fault == NoFault) { @@ -193,8 +193,8 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, - memAccessFlags, NULL); + fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, + NULL); } // Need to write back any potential address register update |