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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 10:33:03 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-12-08 10:33:03 -0800 |
| commit | 7f3f90f71d6993f8a712294e40fe8723bc3d7dbc (patch) | |
| tree | 3ab35474e9c81957e02f3343af6be7bcccc52d70 /src/arch/power/isa/operands.isa | |
| parent | f01d2efe8a106692fd83936d3c6d3565a001616c (diff) | |
| download | gem5-7f3f90f71d6993f8a712294e40fe8723bc3d7dbc.tar.xz | |
POWER: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/power/isa/operands.isa')
| -rw-r--r-- | src/arch/power/isa/operands.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 908e6e0e7..8e13a13d7 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -59,7 +59,8 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), # Program counter and next - 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9), + 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9), + 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9), # Control registers 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), |