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| author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-07-22 18:54:37 +0100 |
|---|---|---|
| committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-07-22 18:54:37 +0100 |
| commit | 97d245278d4b4bee844c141c3b6f370e27f73a45 (patch) | |
| tree | 530c5a892d889d6d6a45dbfbd90bd88500915175 /src/arch/power/miscregs.hh | |
| parent | 607f5198004934c115af7975812a2d69bd005f7e (diff) | |
| download | gem5-97d245278d4b4bee844c141c3b6f370e27f73a45.tar.xz | |
Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.
Diffstat (limited to 'src/arch/power/miscregs.hh')
| -rw-r--r-- | src/arch/power/miscregs.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh index cd9815b2a..34732dad1 100644 --- a/src/arch/power/miscregs.hh +++ b/src/arch/power/miscregs.hh @@ -44,7 +44,12 @@ const char * const miscRegName[NUM_MISCREGS] = { }; BitUnion32(Cr) - Bitfield<31,28> cr0; + SubBitUnion(cr0, 31, 28) + Bitfield<31> lt; + Bitfield<30> gt; + Bitfield<29> eq; + Bitfield<28> so; + EndSubBitUnion(cr0) Bitfield<27,24> cr1; EndBitUnion(Cr) |