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| author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-12 19:53:19 +0000 |
|---|---|---|
| committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-12 19:53:19 +0000 |
| commit | dd60902152321a698682e4f53e29e4043ff321e5 (patch) | |
| tree | 1a3944f6979e79f19de3aedcea36c2817ae507e8 /src/arch/power/tlb.hh | |
| parent | 64999b43435cfee76823e36c23017efc5584b986 (diff) | |
| download | gem5-dd60902152321a698682e4f53e29e4043ff321e5.tar.xz | |
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
Diffstat (limited to 'src/arch/power/tlb.hh')
| -rw-r--r-- | src/arch/power/tlb.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 8b6c7233d..1794de626 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -156,6 +156,8 @@ class TLB : public BaseTLB // static helper functions... really static bool validVirtualAddress(Addr vaddr); static Fault checkCacheability(RequestPtr &req); + Fault translateInst(RequestPtr req, ThreadContext *tc); + Fault translateData(RequestPtr req, ThreadContext *tc, bool write); Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); void translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); |